printf("Write\n");
IOWR(ALTMEMDDR_BASE,0x0000000A,0x11223344);
printf("Reading data\n");
j = IORD(ALTMEMDDR_BASE,0x0000000A);
printf("Data0A: %08x\n" ,j);

Critical Warning: ALTMEMPHY PLL, adcsystem:inst|altmemddr:the_altmemddr|altmemddr_controller_phy:altmemddr_controller_phy_inst|altmemddr_phy:altmemddr_phy_inst|altmemddr_phy_alt_mem_phy:altmemddr_phy_alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_clk_reset:clk|altmemddr_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_n5k3:auto_generated|clk[1], when fed by another PLL, must have bandwidth mode set to High instead of Medium
Critical Warning: ALTMEMPHY PLL, adcsystem:inst|altmemddr:the_altmemddr|altmemddr_controller_phy:altmemddr_controller_phy_inst|altmemddr_phy:altmemddr_phy_inst|altmemddr_phy_alt_mem_phy:altmemddr_phy_alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_clk_reset:clk|altmemddr_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_n5k3:auto_generated|clk[2], when fed by another PLL, must have bandwidth mode set to High instead of Medium
Critical Warning: PLL clock inst|the_altmemddr|altmemddr_controller_phy_inst|altmemddr_phy_inst|altmemddr_ph
y_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source.  To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock inst|the_altmemddr|altmemddr_controller_phy_inst|altmemddr_phy_inst|altmemddr_ph
y_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source.  To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions