outi NVM_CMD,0x02
LPM
mov   r16, r0
STS ADCA_CAL,R16

    ldi r16,PROD_SIGNATURES_START + ADCACAL0_offset
   call SP_ReadCalibrationByte
  sts ADCA.CALL,r16
   ldi r16,PROD_SIGNATURES_START + ADCACAL1_offset
   call SP_ReadCalibrationByte
   sts ADCA.CALH,r16


SP_ReadCalibrationByte:
      ldi    r20, NVM_CMD_READ_CALIB_ROW_gc    ; Prepare NVM command in R20.
      mov    ZL, r16                              ; Load byte index into low byte of Z.
      clr    ZH                                ; Clear high byte of Z.
      sts    NVM_CMD, r20                         ; Load prepared command into NVM Command register.
      lpm   r16, Z                            ; Preform a LPM to read out byte to R16
      ldi    r20, NVM_CMD_NO_OPERATION_gc         ; Clear NVM Command register
      sts    NVM_CMD, r20
      ret

   ldi r16,PROD_SIGNATURES_START + NVM_PROD_SIGNATURES_ADCACAL0_offset
   call SP_ReadCalibrationByte
   sts ADCA_CAL,r16
   ldi r16,PROD_SIGNATURES_START + NVM_PROD_SIGNATURES_ADCACAL1_offset
   call SP_ReadCalibrationByte
   sts ADCA_CAL+1,r16


SP_ReadCalibrationByte:
      ldi    r20, NVM_CMD_READ_CALIB_ROW_gc   ; Prepare NVM command in R20.
      mov    ZL, r16                             ; Load byte index into low byte of Z.
      clr    ZH                               ; Clear high byte of Z.
      sts    NVM_CMD, r20                        ; Load prepared command into NVM Command register.
      lpm   r16, Z                           ; Preform a LPM to read out byte to R16
      ldi    r20, NVM_CMD_NO_OPERATION_gc        ; Clear NVM Command register
      sts    NVM_CMD, r20
ret

ADC_CalibrationValues_Load(&ADCA);
ADC_CalibrationValues_Load(&ADCB);
ADC_ConvMode_and_Resolution_Config(&ADCA, ADC_ConvMode_Unsigned, ADC_RESOLUTION_12BIT_gc);
ADC_ConvMode_and_Resolution_Config(&ADCB, ADC_ConvMode_Unsigned, ADC_RESOLUTION_12BIT_gc);
ADC_Prescaler_Config(&ADCA, ADC_PRESCALER_DIV128_gc);
ADC_Prescaler_Config(&ADCB, ADC_PRESCALER_DIV128_gc);
ADC_Reference_Config(&ADCA, ADC_REFSEL_VCC_gc);
ADC_Reference_Config(&ADCB, ADC_REFSEL_VCC_gc);

ADC_Enable(&ADCA);
ADC_Enable(&ADCB);
ADC_Wait_32MHz(&ADCA);
ADC_Wait_32MHz(&ADCB);

ADC_Ch_InputMode_and_Gain_Config(&ADCA.CH0, ADC_CH_INPUTMODE_SINGLEENDED_gc, ADC_CH_GAIN_1X_gc);
ADC_Ch_InputMode_and_Gain_Config(&ADCA.CH1, ADC_CH_INPUTMODE_SINGLEENDED_gc, ADC_CH_GAIN_1X_gc);
ADC_Ch_InputMode_and_Gain_Config(&ADCA.CH2, ADC_CH_INPUTMODE_SINGLEENDED_gc, ADC_CH_GAIN_1X_gc);
ADC_Ch_InputMode_and_Gain_Config(&ADCA.CH3, ADC_CH_INPUTMODE_SINGLEENDED_gc, ADC_CH_GAIN_1X_gc);
// adcB
ADC_Ch_InputMode_and_Gain_Config(&ADCB.CH0, ADC_CH_INPUTMODE_SINGLEENDED_gc, ADC_CH_GAIN_1X_gc);
ADC_Ch_InputMode_and_Gain_Config(&ADCB.CH1, ADC_CH_INPUTMODE_SINGLEENDED_gc, ADC_CH_GAIN_1X_gc);
ADC_Ch_InputMode_and_Gain_Config(&ADCB.CH2, ADC_CH_INPUTMODE_SINGLEENDED_gc, ADC_CH_GAIN_1X_gc);
ADC_Ch_InputMode_and_Gain_Config(&ADCB.CH3, ADC_CH_INPUTMODE_SINGLEENDED_gc, ADC_CH_GAIN_1X_gc);

/// пауза
unsigned short adc_result;
unsigned short adc[4];
for (i=0; i<4; i++) {
adc[i]=adc_ch_ptr->RES;
}