logic [15:0] mem [2**12 : 0];

logic [15:0] rg_ram_rd;

always_ff @(posedge iclk) begin
    if     (!EMA_WEn && !EMA_CS2) mem[EMA_ADR]<=EMA_DATA;
end

always_ff @(posedge iclk) begin
    if     (!EMA_OEn && !EMA_CS2) rg_ram_rd<=mem[EMA_ADR];
end

library ieee;
use ieee.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;
entity ram_dual is
    port
        (
        data    : in std_logic_vector(7 downto 0);
        raddr    : in std_logic_vector(3 downto 0);
        waddr    : in std_logic_vector(2 downto 0);
        we        : in std_logic := '1';
        re        : in std_logic := '1';
        clk        : in std_logic;
        q        : out std_logic_vector(3 downto 0)
        );
end ram_dual;

architecture rtl of ram_dual is
    attribute syn_ramstyle : string;
    attribute syn_ramstyle of rtl : architecture is "M-RAM";
    
    -- Build a 2-D array type for the RAM
    subtype word is std_logic_vector(7 downto 0);
    subtype nibble is std_logic_vector(3 downto 0);
    
    type mem_A is array(8 downto 0) of word;
    type mem_B is array(15 downto 0) of nibble;
    -- Declare the RAM signal.
    signal ram_A : mem_A;
    signal ram_B : mem_B;
    shared variable j: integer RANGE 0 TO 15;
begin
    
    process(clk)
    begin
        if(rising_edge(clk)) then
            if(we = '1') then
                ram_A(CONV_INTEGER (waddr)) <= data;
            end if;
        end if;
    end process;
    
    process(clk)
    begin
        if rising_edge(clk) then
            --j:=0;
            for i in 0 to 7 loop
                for k in 0 to 1 loop
                    if k = 0 then    ram_B(j)<=ram_A(i)(7 downto 4);
                    else             ram_B(j)<=ram_A(i)(3 downto 0);
                    end if;
                    j:=j+1;
                end loop;
            end loop;
        
            if (re = '1') then
                q(3 downto 0) <= ram_B(CONV_INTEGER(raddr));
            end if;    
        end if;    
    end process;
    
end rtl;