1. В одном из документов Alterы написано:
«Read Access
Read access from an external PHY can be done using the MDIO interface as follows:
1. Perform an Avalon-MM master write to the MDIO core registers at address offset 0x21, specifying the external PHY device address (MDIO_DEVAD), port-address (MDIO_PRTAD) and register address (MDIO_REGAD).
2. Issue an Avalon-MM master read of the 32-bit MDIO_ACCESS register at offset 0x20.
What happens in the MDIO core?
When a read access to the MDIO_ACCESS register is issued, the MDIO core starts the generation of an MDIO READ frame that contains the information provided in the registers at offset 0x21. As a response to this READ command over MDIO, the external PHY provides the value of the designated register back to the MDIO core. This value is loaded into the MDIO_ACCESS register in the MDIO core at offset 0x20. Thus, it appears as though we were reading the local Avalon-MM register at offset 0x20.»
В связи с этим возникли вопросы:
1. Какое устройство должно выступать в роли Avalon-MM master в п.2? CPU?
2. Какова вообще должна быть структура проекта Quartus для управления устройством 88Е1111 c помощью MDIO? (Т.е. какие компоненты должны входить в проект?)
Заранее спасибо.