LIBRARY ieee;    

    use IEEE.Std_logic_1164.all;                
    use IEEE.Std_logic_unsigned.all;
    use IEEE.std_logic_arith.all;
    use IEEE.numeric_std.all;


ENTITY LAN_drv IS        
    
    PORT    
        (
            RESET                  : in    std_logic;
            CLK_20_MHz_72      : in    std_logic;
            Bt_IN                  : in    std_logic_vector (7 downto 0);
            
            ADR_OUT                : out    std_logic_vector (7 downto 0);
            DATA_LAN1_INOUT    : inout    std_logic_vector (15 downto 0);
            WR_LAN1_OUT            : out    std_logic;
            RD_LAN1_OUT            : out    std_logic;
            CS_LAN1_OUT            : out    std_logic

        );
    END LAN_drv;

ARCHITECTURE arhitektura OF LAN_drv IS
signal         ADR_LO_TX_CFG            : std_logic_vector(7 downto 0):= X"70";
signal         ADR_HI_TX_CFG            : std_logic_vector(7 downto 0):= X"71";
signal         ADR_LO_GPIO_CFG        : std_logic_vector(7 downto 0):= X"88";
signal         ADR_HI_GPIO_CFG        : std_logic_vector(7 downto 0):= X"89";
signal         LO_WORD_TX_CFG        : std_logic_vector (15 downto 0):= X"0003";
signal         HI_WORD_TX_CFG        : std_logic_vector (15 downto 0):= X"0000";
signal         LO_WORD_GPIO_CFG    : std_logic_vector (15 downto 0):= X"0000";
signal         HI_WORD_GPIO_CFG    : std_logic_vector (15 downto 0):= X"7000";

signal         BUF_DATA_OUT        : std_logic_vector (15 downto 0);
signal         BUF_ADR_OUT            : std_logic_vector (7 downto 0);
signal         sel                    : std_logic_vector (1 downto 0);

signal         CS_LAN1                : std_logic := '1';
signal         WR_LAN1                : std_logic := '1';
signal         RD_LAN1                : std_logic := '1';

signal         WR_RD_count            : integer range 0 to 3;
signal         count_bit            : std_logic_vector (3 downto 0);

    BEGIN
SEL(1 downto 0) <= BT_IN(1 downto 0);
CS_LAN1_OUT <= CS_LAN1;
WR_LAN1_OUT <= WR_LAN1;
RD_LAN1_OUT <= RD_LAN1;
ADR_OUT <= BUF_ADR_OUT;
DATA_LAN1_INOUT <= BUF_DATA_OUT when WR_LAN1 = '0' else "ZZZZZZZZZZZZZZZZ";

        PROCESS (CLK_20_MHz_72, WR_RD_count, SEL, RESET)
            BEGIN
                if WR_RD_count = 2 or RESET = '0' then CS_LAN1 <= '1';
                elsif CLK_20_MHz_72'EVENT and CLK_20_MHz_72 = '1' THEN
                    if SEL /= "11" and WR_RD_count = 0 then CS_LAN1 <= '0';
                    end if;
                end if;
            END PROCESS;
WR_LAN1 <= CS_LAN1 or CLK_20_MHz_72;

        PROCESS (WR_LAN1, SEL)
            BEGIN
                if SEL = "11" then WR_RD_count <= 0;
                elsif WR_LAN1'EVENT and WR_LAN1 = '1' THEN
                    WR_RD_count <= WR_RD_count + 1;
                end if;
            END PROCESS;            

        PROCESS (CLK_20_MHz_72, WR_RD_count, SEL)
            BEGIN
                if CLK_20_MHz_72'EVENT and CLK_20_MHz_72 = '0' THEN
                        case SEL is
                            when "10" =>
                                if WR_RD_count = 0 Then BUF_ADR_OUT <= ADR_LO_TX_CFG; BUF_DATA_OUT <= LO_WORD_TX_CFG;
                                    else BUF_ADR_OUT <= ADR_HI_TX_CFG; BUF_DATA_OUT <= HI_WORD_TX_CFG;
                                end if;
                            
                            when "01" =>
                                if WR_RD_count = 0 Then BUF_ADR_OUT <= ADR_LO_GPIO_CFG; BUF_DATA_OUT <= LO_WORD_GPIO_CFG;
                                    else BUF_ADR_OUT <= ADR_HI_GPIO_CFG; BUF_DATA_OUT <= HI_WORD_GPIO_CFG;
                                end if;
                            
                            when others => BUF_DATA_OUT <= X"0000"; BUF_ADR_OUT <=X"00";
                        end case;
                end if;
            END PROCESS;

            
END arhitektura;