NVIC->ISER[(DMA2_Stream0_IRQn >> 0x05)] = (u32)0x01 << (DMA2_Stream0_IRQn & (u8)0x1F); /* Enable DMA interrupt */

RCC->APB2ENR |= (1<<8);

RCC->AHB1ENR |= (1<<22); // DMA1EN
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // Ðàçðåøèòü òàêòèðîâàíèå PORTE.

ADC1->CR1 |= ADC_CR1_AWDIE| // AWD on injected channels whith interrupt
ADC_CR1_SCAN; // Scan mode + auto injection
ADC1->SMPR2 = 0x0000; // 1.5 sampling time
ADC1->SQR1 = 0x00; // 1 conversion

ADC1->SQR3 = ADC_SQR3_SQ1_3; // 8 chanell

ADC1->CR2 = ADC_CR2_EXTSEL_0 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_2 // run SWSTART
//| ADC_CR2_EXTEN
| ADC_CR2_DMA
| ADC_CR2_CONT; // enable externall run


ADC1->SMPR1 = 0x0920000B;

GPIOB->MODER |= (GPIO_MODER_MODER0); // PORTB.0 Analog input


// DMA configuring
DMA2_Stream0->CR |= DMA_SxCR_PL | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 |
//Hight pry, 16 byte mem, 16 byte pereph
DMA_SxCR_MINC |
//DMA_CCR1_CIRC|
DMA_SxCR_HTIE |
DMA_SxCR_TCIE; // mem inc, circular, enterrupts by Half and End of conv

DMA2_Stream0->NDTR = ADC_ARRAY_SIZE;
DMA2_Stream0->PAR = (uint32_t)&ADC1->DR;
DMA2_Stream0->M0AR = (uint32_t)&TOK_HI[0];
// On converting
ADC1->CR2 |= ADC_CR2_ADON; // Adc ON
// Additional delay to Vref on


DMA2_Stream0->CR &= ~DMA_SxCR_EN; /* Disable DMA */
DMA2_Stream0->NDTR = ADC_ARRAY_SIZE;
DMA2_Stream0->CR |= DMA_SxCR_EN; /* Enable DMA */
ADC1->CR2 |= ADC_CR2_SWSTART;

    
    DMA2_Stream0->CR &= ~DMA_SxCR_EN; // Disable DMA
    DMA2->LIFCR |= ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<5));
    DMA2_Stream0->NDTR = ADC_ARRAY_SIZE;
    DMA2_Stream0->CR |= DMA_SxCR_EN; //Enable DMA

void TIM1_CC_IRQHandler(void)
{

if (TIM1->SR & TIM_SR_CC3IF)
{
DMA2_Stream0->CR &= ~DMA_SxCR_EN; // Disable DMA

DMA2->LIFCR |= ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<5));
DMA2_Stream0->CR ^= DMA_SxCR_CT; // switch buffer
if (DMA2_Stream0->CR & DMA_SxCR_CT)
setBuf = 1;
DMA2_Stream0->NDTR = ADC_ARRAY_SIZE;
DMA2_Stream0->CR |= DMA_SxCR_EN; //Enable DMA
ADC1->CR2 |= ADC_CR2_ADON;
ADC1->CR2 |= ADC_CR2_SWSTART;


//******************************************************************************
// *************** копируем данные в буфер для вывода графика ******************
//******************************************************************************
if (grFlag == 1)
{

DMA2_Stream1->NDTR = 93;
if (DMA2_Stream0->CR & DMA_SxCR_CT)
DMA2_Stream1->PAR = (uint32_t)&TOK_HI_0[0];
else
DMA2_Stream1->PAR = (uint32_t)&TOK_HI_1[0];
DMA2->LIFCR |= ((1<<6)|(1<<8)|(1<<9)|(1<<10)|(1<<11));
DMA2_Stream1->M0AR = (uint32_t)&GR_BUFF[indexGR];
DMA2_Stream1->CR |= DMA_SxCR_EN; //Enable DMA
indexGR += 93;
}

}
}