Цитата(vitan @ Aug 23 2012, 16:00)

Lmx2315
1.Бла-бла-бла это что конкретно?
2. Ставьте 16.5, зачем такие странности?
Error: netrev failed. Unable to export design.
Do you wish to view the netrev.lst file?
16.5 под рукой нет, да и к томуже - я его не смог поставить . 16.3 чудом заработал.
вставить файл не смог - почему-то запрещено.
(---------------------------------------------------------------------)
( )
( Netrev Allegro Import Logic )
( )
( Drawing : analog_m7_v9_payka_test.brd )
( Software Version : 16.3p004 )
( Date/Time : Thu Aug 23 15:20:18 2012 )
( )
(---------------------------------------------------------------------)
------ Directives ------
RIPUP_ETCH TRUE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'C:\PSD_data\Projects\B600\worklib\analog_m5\packaged';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'C:/PSD_data/Projects/B600/worklib/analog_m5/physical/analog_m7_v9_payka_test.brd';
NEW_BOARD_NAME 'C:/PSD_data/Projects/B600/worklib/analog_m5/physical/analog_m7_v9_payka_test.brd';
CmdLine: netrev -proj C:\PSD_data\Projects\B600\trudolubie.cpm -5 -y 1 -x -u -z -Oo C:\PSD_data\Projects\B600\worklib\analog_m5\physical\analog_m7_v9_payka_test.brd C:\PSD_data\Projects\B600\worklib\analog_m5\physical\analog_m7_v9_payka_test.brd -$
------ Preparing to read pst files ------
Starting to read C:/PSD_data/Projects/B600/worklib/analog_m5/packaged/pstchip.dat
Finished reading C:/PSD_data/Projects/B600/worklib/analog_m5/packaged/pstchip.dat (00:00:00.29)
Starting to read C:/PSD_data/Projects/B600/worklib/analog_m5/packaged/pstxprt.dat
Finished reading C:/PSD_data/Projects/B600/worklib/analog_m5/packaged/pstxprt.dat (00:00:00.01)
Starting to read C:/PSD_data/Projects/B600/worklib/analog_m5/packaged/pstxnet.dat
Finished reading C:/PSD_data/Projects/B600/worklib/analog_m5/packaged/pstxnet.dat (00:00:00.01)
------ Oversights/Warnings/Errors ------
Note: PHYS_PAGE property definition created
------ Library Paths ------
MODULEPATH = .
C:/Cadence/SPB_16.3/share/local/pcb/modules
PSMPATH = C:\PSD_data\footprints\SYMBOLS\
C:\PSD_data\My_symbols\
C:\PSD_data\PADSTACKS\
C:\Cadence\SPB_15.2\share\pcb\pcb_lib\symbols
PADPATH = .
symbols
..
../symbols
C:/Cadence/SPB_16.3/share/local/pcb/padstacks
C:/Cadence/SPB_16.3/share/pcb/pcb_lib/symbols
C:/Cadence/SPB_16.3/share/pcb/allegrolib/symbols
C:\PSD_data\PADSTACKS\
C:\PSD_data\SYMBOLS\
C:\Cadence\SPB_15.2\share\pcb\pcb_lib\symbols
C:\PSD_data\My_symbols\
===========================================================
Start Constraint Override Import
Constraint File: C:/PSD_data/Projects/B600/worklib/analog_m5/packaged/pstcmdb.dat
Start time: Thu Aug 23 15:20:18 2012
===========================================================
===========================================================
Finished Constraint Update Time: Thu Aug 23 15:20:18 2012
===========================================================
------ Summary Statistics ------
netrev run on Aug 23 15:20:17 2012
DESIGN NAME : 'ANALOG_M5'
PACKAGING ON 23-Aug-2012 AT 15:20:14
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
DIRECTORIES <none>
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
LIBRARIES 'trudolubie_lib' 'discrete_niitp' 'import_lib' 'leds_niitp'
'logic_niitp' 'max_niitp' 'standard' 'supervisor_niitp'
'interfeysnaya' 'power_my' 'power_niitp' 'my_passive_niitp' 'pll'
'vco' 'power_divider' 'attenuator' 'rf_amplifer' 'ldo' 'vcxo'
'rbu' 'bushprit' 'my_connectors_niitp' 'my_memory_niitp'
'my_supervisory_niitp' 'my_leds_niitp' 'my_transceiver' 'bdv_lib'
'b620'
MASTER_LIBRARIES <none>
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
No error detected
No oversight detected
No warning detected
cpu time 0:02:30
elapsed time 0:00:01