probe called: device is c01d51a8
Epson S1D13XXX FB Driver
s1d13xxxfb: unknown chip production id 0, revision 0
s1d13xxxfb: please contant maintainer

probe called: device is c01d51a8
Epson S1D13XXX FB Driver
s1d13xxxfb: prod_id = 0, s1d13xxxfb_prod_ids = 3
s1d13xxxfb: prod_id = 0, s1d13xxxfb_prod_ids = 4
s1d13xxxfb: prod_id = 0, s1d13xxxfb_prod_ids = 7
s1d13xxxfb: unknown chip production id 0, revision 0
s1d13xxxfb: please contant maintainer

<------>/* production id is top 6 bits */
prod_id = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) >> 2;
<------>/* revision id is lower 2 bits */
revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) & 0x3;

#define EPSONREGSTART 0x93000000
#define EPSONREGLEN 0x00100000
#define EPSONFBSTART 0x93200000
/* 512kB framebuffer */
#define EPSONFBLEN 512*1024


static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
/* line 344 of HP's doc */
{0x0000,0x04}, // Prod + Rev Code Register
{0x0001,0x00}, // Miscellaneous Register
{0x01FC,0x00}, // Display Mode Register
{0x0004,0x00}, // General IO Pins Configuration Register 0
{0x0005,0x00}, // General IO Pins Configuration Register 1
{0x0008,0x00}, // General IO Pins Control Register 0
{0x0009,0x00}, // General IO Pins Control Register 1
{0x0010,0x01}, // Memory Clock Configuration Register
{0x0014,0x11}, // LCD Pixel Clock Configuration Register
{0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
{0x001C,0x01}, // MediaPlug Clock Configuration Register
{0x001E,0x01}, // CPU To Memory Wait State Select Register
{0x0020,0x00}, // Memory Configuration Register
{0x0021,0x45}, // DRAM Refresh Rate Register
{0x002A,0x01}, // DRAM Timings Control Register 0
{0x002B,0x03}, // DRAM Timings Control Register 1
{0x0030,0x1c}, // Panel Type Register
{0x0031,0x00}, // MOD Rate Register
{0x0032,0x4F}, // LCD Horizontal Display Width Register
{0x0034,0x07}, // LCD Horizontal Non-Display Period Register
{0x0035,0x01}, // TFT FPLINE Start Position Register
{0x0036,0x0B}, // TFT FPLINE Pulse Width Register
{0x0038,0xEF}, // LCD Vertical Display Height Register 0
{0x0039,0x00}, // LCD Vertical Display Height Register 1
{0x003A,0x13}, // LCD Vertical Non-Display Period Register
{0x003B,0x0B}, // TFT FPFRAME Start Position Register
{0x003C,0x01}, // TFT FPFRAME Pulse Width Register
{0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
{0x0041,0x00}, // LCD Miscellaneous Register
{0x0042,0x00}, // LCD Display Start Address Register 0
{0x0043,0x00}, // LCD Display Start Address Register 1
{0x0044,0x00}, // LCD Display Start Address Register 2
{0x0046,0x80}, // LCD Memory Address Offset Register 0
{0x0047,0x02}, // LCD Memory Address Offset Register 1
{0x0048,0x00}, // LCD Pixel Panning Register
{0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
{0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
{0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
{0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
{0x0053,0x01}, // CRT/TV HRTC Start Position Register
{0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
{0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
{0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
{0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
{0x0059,0x09}, // CRT/TV VRTC Start Position Register
{0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
{0x005B,0x10}, // TV Output Control Register
{0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
{0x0062,0x00}, // CRT/TV Display Start Address Register 0
{0x0063,0x00}, // CRT/TV Display Start Address Register 1
{0x0064,0x00}, // CRT/TV Display Start Address Register 2
{0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
{0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
{0x0068,0x00}, // CRT/TV Pixel Panning Register
{0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
{0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
{0x0070,0x00}, // LCD Ink/Cursor Control Register
{0x0071,0x01}, // LCD Ink/Cursor Start Address Register
{0x0072,0x00}, // LCD Cursor X Position Register 0
{0x0073,0x00}, // LCD Cursor X Position Register 1
{0x0074,0x00}, // LCD Cursor Y Position Register 0
{0x0075,0x00}, // LCD Cursor Y Position Register 1
{0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
{0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
{0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
{0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
{0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
{0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
{0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
{0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
{0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
{0x0082,0x00}, // CRT/TV Cursor X Position Register 0
{0x0083,0x00}, // CRT/TV Cursor X Position Register 1
{0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
{0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
{0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
{0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
{0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
{0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
{0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
{0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
{0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
{0x0100,0x00}, // BitBlt Control Register 0
{0x0101,0x00}, // BitBlt Control Register 1
{0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
{0x0103,0x00}, // BitBlt Operation Register
{0x0104,0x00}, // BitBlt Source Start Address Register 0
{0x0105,0x00}, // BitBlt Source Start Address Register 1
{0x0106,0x00}, // BitBlt Source Start Address Register 2
{0x0108,0x00}, // BitBlt Destination Start Address Register 0
{0x0109,0x00}, // BitBlt Destination Start Address Register 1
{0x010A,0x00}, // BitBlt Destination Start Address Register 2
{0x010C,0x00}, // BitBlt Memory Address Offset Register 0
{0x010D,0x00}, // BitBlt Memory Address Offset Register 1
{0x0110,0x00}, // BitBlt Width Register 0
{0x0111,0x00}, // BitBlt Width Register 1
{0x0112,0x00}, // BitBlt Height Register 0
{0x0113,0x00}, // BitBlt Height Register 1
{0x0114,0x00}, // BitBlt Background Color Register 0
{0x0115,0x00}, // BitBlt Background Color Register 1
{0x0118,0x00}, // BitBlt Foreground Color Register 0
{0x0119,0x00}, // BitBlt Foreground Color Register 1
{0x01E0,0x00}, // Look-Up Table Mode Register
{0x01E2,0x00}, // Look-Up Table Address Register
/* not sure, wouldn't like to mess with the driver */
{0x01E4,0x00}, // Look-Up Table Data Register
/* jornada doc says 0x00, but I trust the driver */
{0x01F0,0x10}, // Power Save Configuration Register
{0x01F1,0x00}, // Power Save Status Register
{0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
{0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
};


static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
.initregs = s1d13xxxfb_initregs,
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
.platform_init_video = NULL
};

static struct resource s1d13xxxfb_resources[] = {
[0] = {
.start = EPSONFBSTART,
.end = EPSONFBSTART + EPSONFBLEN,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = EPSONREGSTART,
.end = EPSONREGSTART + EPSONREGLEN,
.flags = IORESOURCE_MEM,
}
};

static struct platform_device s1d13xxxfb_device = {
.name = S1D_DEVICENAME,
.id = 0,
.dev = {
.platform_data = &s1d13xxxfb_data,
},
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
.resource = s1d13xxxfb_resources,
};

static struct platform_device *devices[] __initdata = {
&s1d13xxxfb_device,
};


static int __init spmp_displ_init(void)
{


int ret = -ENODEV;
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
return ret;
}

arch_initcall(spmp_displ_init);

835         if (pdata && pdata->platform_init_video)
836                 pdata->platform_init_video();

Epson S1D13XXX FB Driver
Trying to free nonexistent resource <0000000093000000-0000000093100000>

<------>axi {
<------><------>compatible = "simple-bus";
<------><------>#address-cells = <1>;
<------><------>#size-cells = <1>;
<------><------>ranges = <0x93000000 0x93000000 0x800000>;

<------><------>fb@93000000 {
<------><------><------>compatible = "sunplus,spmp8000-lcd";
<------><------><------>reg = <0x93000000 0x1000>;
<------><------><------>interrupt-parent = <&vic0>;
<------><------><------>interrupts = <23>;
<------><------>};

<------><------>axi-apb {
<------><------><------>compatible = "simple-bus";
<------><------><------>#address-cells = <1>;
<------><------><------>#size-cells = <1>;
<------><------><------>ranges = <0x93010000 0x93010000 0x10000>;

<------><------><------>dma@93010000 {
<------><------><------><------>compatible = "sunplus,spmp8000-apbdma-a";
<------><------><------><------>reg = <0x93010000 0x1000>;
<------><------><------><------>interrupt-parent = <&vic0>;
<------><------><------><------>interrupts = <24 25 26 27>;
<------><------><------>};

<------><------><------>i2s@93012000 {
<------><------><------><------>compatible = "sunplus,spmp8000-i2s-tx";
<------><------><------><------>reg = <0x93012000 0x1000>;
<------><------><------><------>interrupt-parent = <&vic0>;
<------><------><------><------>interrupts = <13>;
<------><------><------>};

<------><------><------>i2s@9301D000 {
<------><------><------><------>compatible = "sunplus,spmp8000-i2s-rx";
<------><------><------><------>reg = <0x9301D000 0x1000>;
<------><------><------><------>interrupt-parent = <&vic0>;
<------><------><------><------>interrupts = <14>;
<------><------><------>};

<------><------><------>adc@9301F000 {
<------><------><------><------>compatible = "sunplus,spmp8000-adc";
<------><------><------><------>reg = <0x9301F000 0x20>;
<------><------><------><------>interrupt-parent = <&vic1>;
<------><------><------><------>interrupts = <27>;
<------><------><------>};

<------><------><------>codec@9301F020 {
<------><------><------><------>compatible = "sunplus,spmp8000-codec";
<------><------><------><------>reg = <0x9301F020 0x20>;
<------><------><------>};
<------><------>};
<------>};

<------>OF_DEV_AUXDATA("pwm-backlight", 0, "pwm-backlight",
<------><------><------>&backlight_letcool),
<------>OF_DEV_AUXDATA("sunplus,spmp8000-lcd", 0x93000000, "93000000.fb",
<------><------><------>&spmp8000fb_letcool),

// SPMP8000 LCD controller

typedef lcd_info_ctx {
uint32_t flags; // 0x00
uint16_t width; // 0x04
uint16_t height; // 0x06
uint16_t // 0x08
uint16_t // 0x0A
uint32_t frm_buff; // 0x0c
uint16_t osd_width; // 0x10
uint16_t osd_height; // 0x12

uint32_t osd_buff; // 0x18
uint8_t // 0x1c
uint8_t // 0x1d
}

setLCDFrameBuffer:
LDR R3, =lcd_info_ctx
STR R0, [R3,#0xC]
MOVL R3, 0x93000054
STR R0, [R3]
LDR R3, =lcd_direct_update
LDR R3, [R3]
CMP R3, #0
MOVLNE R3, 0x93000078
MOVNE R2, #1
STRNE R2, [R3]
BX LR

// void cyg_interrupt_create(cyg_vector_t vector, cyg_priority_t priority, cyg_addrword_t data, cyg_ISR_t* isr,
// cyg_DSR_t* dsr, cyg_handle_t* handle, cyg_interrupt* intr);

0029965C lcd_gen_init

00298CFC lcd_init2(width, height)
cyg_interrupt_create(0x17, 10, ???, lcd_isr_default)
-> 00297AF4 lcd_isr_default

002978C8 LCDC_S110_init
002972A8 hal_lcd_init
00292A74 scu_lcd_enable(freq_div_factor)

002995D0 lcd_suspend
00299514 lcd_resume

00298E68 osd_init2
00297870 OSDC_S110_init


LCDC_BASE 0x93000000

#define LCDC_CTRL (LCDC_BASE + 0x00) // write 0x10000
#define LCDC_UNK1 (LCDC_BASE + 0x04)
#define LCDC_UNK2 (LCDC_BASE + 0x08) // lcd_info_ctx[10]
#define LCDC_HOR_FBLK (LCDC_BASE + 0x0c)
#define LCDC_HOR_BBLK (LCDC_BASE + 0x14)
#define LCDC_HOR_SYNCW (LCDC_BASE + 0x28)
#define LCDC_VER_FBLK (LCDC_BASE + 0x18)
#define LCDC_VER_BBLK (LCDC_BASE + 0x1c)
#define LCDC_VER_SYNCW (LCDC_BASE + 0x2c)

.text:002D30B4 LDR R3, =gFrameBufferMgr ; param_R2
.text:002D30B8 LDR R2, =set_lcd_fb_format
.text:002D30BC STR R2, [R3]
.text:002D30C0 LDR R2, =getLCDBuffFormat
.text:002D30C4 STR R2, [R3,#4]
.text:002D30C8 LDR R2, =getLCDWidth
.text:002D30CC STR R2, [R3,#8]
.text:002D30D0 LDR R2, =getLCDHeight
.text:002D30D4 STR R2, [R3,#0xC]
.text:002D30D8 LDR R2, =getLCDShadowBuffer
.text:002D30DC STR R2, [R3,#0x10]
.text:002D30E0 LDR R2, =getLCDFrameBuffer
.text:002D30E4 STR R2, [R3,#0x14]
.text:002D30E8 LDR R2, =setLCDFrameBuffer
.text:002D30EC STR R2, [R3,#0x18]
.text:002D30F0 LDR R2, =lcd_flip
.text:002D30F4 STR R2, [R3,#0x1C]
.text:002D30F8 LDR R2, =lcd_gen_init
.text:002D30FC STR R2, [R3,#0x20]
.text:002D3100 LDR R2, =lcd_clear
.text:002D3104 STR R2, [R3,#0x24]
.text:002D3108 LDR R2, =wait_lcd_frame_end
.text:002D310C STR R2, [R3,#0x28]
.text:002D3110 LDR R2, =setLCDShadowBuffer
.text:002D3114 STR R2, [R3,#0x2C]
.text:002D3118 LDR R2, =lcd_suspend
.text:002D311C STR R2, [R3,#0x30]
.text:002D3120 LDR R2, =lcd_resume
.text:002D3124 STR R2, [R3,#0x34]
.text:002D3128 LDR R2, =lcd_enable_layer_no_osd
.text:002D312C STR R2, [R3,#0x38]
.text:002D3130 LDR R2, =lcd_set_bright_level ; param_R1
.text:002D3134 STR R2, [R3,#0x3C]
.text:002D3138 B loc_2D3264
.text:002D313C ; ---------------------------------------------------------------------------
.text:002D313C
.text:002D313C loc_2D313C ; CODE XREF: setFrameBufferMgr+4Cj
.text:002D313C LDR R0, =aSetframebuff_1 ; int
.text:002D3140 BL diag_printf
.text:002D3144 LDR R3, =gFrameBufferMgr ; param_R2
.text:002D3148 LDR R2, =set_osd_fb_format
.text:002D314C STR R2, [R3]
.text:002D3150 LDR R2, =getOSDBuffFormat
.text:002D3154 STR R2, [R3,#4]
.text:002D3158 LDR R2, =getOSDWidth
.text:002D315C STR R2, [R3,#8]
.text:002D3160 LDR R2, =getOSDHeight
.text:002D3164 STR R2, [R3,#0xC]
.text:002D3168 LDR R2, =getOSDShadowBuffer
.text:002D316C STR R2, [R3,#0x10]
.text:002D3170 LDR R2, =getOSDFrameBuffer
.text:002D3174 STR R2, [R3,#0x14]
.text:002D3178 LDR R2, =setOSDFrameBuffer
.text:002D317C STR R2, [R3,#0x18]
.text:002D3180 LDR R2, =lcd_osd_flip
.text:002D3184 STR R2, [R3,#0x1C]
.text:002D3188 LDR R2, =lcd_gen_init
.text:002D318C STR R2, [R3,#0x20]
.text:002D3190 LDR R2, =lcd_osd_clear
.text:002D3194 STR R2, [R3,#0x24]
.text:002D3198 LDR R2, =wait_lcd_frame_end
.text:002D319C STR R2, [R3,#0x28]
.text:002D31A0 LDR R2, =setOSDShadowBuffer
.text:002D31A4 STR R2, [R3,#0x2C]
.text:002D31A8 LDR R2, =lcd_suspend
.text:002D31AC STR R2, [R3,#0x30]
.text:002D31B0 LDR R2, =lcd_resume
.text:002D31B4 STR R2, [R3,#0x34]
.text:002D31B8 LDR R2, =lcd_enable_layer
.text:002D31BC STR R2, [R3,#0x38]
.text:002D31C0 LDR R2, =lcd_set_bright_level ; param_R1
.text:002D31C4 STR R2, [R3,#0x3C]
.text:002D31C8 B loc_2D3264
.text:002D31CC ; ---------------------------------------------------------------------------
.text:002D31CC
.text:002D31CC loc_2D31CC ; CODE XREF: setFrameBufferMgr+40j
.text:002D31CC LDR R0, =aSetframebuff_2 ; int
.text:002D31D0 BL diag_printf
.text:002D31D4 MOV R2, #2
.text:002D31D8 LDR R3, =g_FrameBuffDev
.text:002D31DC STR R2, [R3]
.text:002D31E0 LDR R3, =gFrameBufferMgr
.text:002D31E4 LDR R2, =set_tv_osd_fb_format
.text:002D31E8 STR R2, [R3]
.text:002D31EC LDR R2, =get_tv_osd_BuffFormat
.text:002D31F0 STR R2, [R3,#4]
.text:002D31F4 LDR R2, =get_tv_osd_width
.text:002D31F8 STR R2, [R3,#8]
.text:002D31FC LDR R2, =get_tv_osd_height
.text:002D3200 STR R2, [R3,#0xC]
.text:002D3204 LDR R2, =get_tv_osd_ShadowBuffer
.text:002D3208 STR R2, [R3,#0x10]
.text:002D320C LDR R2, =get_tv_osd_FrameBuffer
.text:002D3210 STR R2, [R3,#0x14]
.text:002D3214 LDR R2, =set_tv_osd_FrameBuffer
.text:002D3218 STR R2, [R3,#0x18]
.text:002D321C LDR R2, =tv_osd_flip
.text:002D3220 STR R2, [R3,#0x1C]
.text:002D3224 LDR R2, =tv_gen_init
.text:002D3228 STR R2, [R3,#0x20]
.text:002D322C LDR R2, =tv_osd_clear
.text:002D3230 STR R2, [R3,#0x24]
.text:002D3234 LDR R2, =tv_out_wait_frame_end
.text:002D3238 STR R2, [R3,#0x28]
.text:002D323C LDR R2, =set_tv_osd_ShadowBuffer
.text:002D3240 STR R2, [R3,#0x2C]
.text:002D3244 LDR R2, =tv_suspend
.text:002D3248 STR R2, [R3,#0x30]
.text:002D324C LDR R2, =tv_resume
.text:002D3250 STR R2, [R3,#0x34]
.text:002D3254 LDR R2, =tv_enable_layer
.text:002D3258 STR R2, [R3,#0x38]
.text:002D325C LDR R2, =tv_set_bright_level
.text:002D3260 STR R2, [R3,#0x3C]
.text:002D3264
.text:002D3264 loc_2D3264 ; CODE XREF: setFrameBufferMgr+50j
.text:002D3264 ; setFrameBufferMgr+58j ...
.text:002D3264 BL cyg_scheduler_unlock
.text:002D3268 LDR R0, =aSetframebuff_3 ; int
.text:002D326C BL diag_printf
.text:002D3270 LDMFD SP, {R4,R11,SP,PC}
.text:002D3270 ; End of function setFrameBufferMgr

EXPORT scu_set_disp_clk
scu_set_disp_clk
; CODE XREF: scu_lcm_enable+10^Yp
; scu_lcd_enable+4^Yp ...
LDR R2, =0x93007000 ;задать регистру Р2 адрес 0x93007000
LDR R3, [R2,#0x80] ;косвенно считать в регистр Р3 содержимое памяти по адресу Р2+смещение 0x80
BIC R3, R3, #0x100
STR R3, [R2,#0x80]
BIC R3, R3, #0xFF
SUB R0, R0, #1
ORR R0, R0, R3
STR R0, [R2,#0x80]
ORR R0, R0, #0x100
STR R0, [R2,#0x80]
BX LR
; End of function scu_set_disp_clk

#define SPMP8000_SCU_A_BASE 0x93007000
#define SCU_A_LCD_CLK_CFG 0x80