LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY lpm_counter0 IS
    PORT
    (
        clk        : IN STD_LOGIC;
        q        : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
    );
END lpm_counter0;


ARCHITECTURE SYN OF lpm_counter0 IS

    SIGNAL summ    : STD_LOGIC_VECTOR (3 DOWNTO 0);
    signal equal : STD_LOGIC;
    signal updown : STD_LOGIC;
begin
    
    q <= summ;
    equal <= '1' when summ = "1111" or summ = "0000" else '0';
    updown <= not updown when rising_edge(equal);
    
process(clk)
    begin
    if rising_edge(clk) and updown = '0' then
        summ <= summ + "0001";
    elsif rising_edge(clk) and updown = '1' then
        summ <= summ - "0001";
    end if;
end process;



END SYN;