LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY spi_slave IS
  GENERIC(
    d_width : INTEGER := 12);     --data width in bits
  PORT
    (
        Clk         : IN    STD_LOGIC;-- := '0';
        Shift       : IN    STD_LOGIC;-- := '0';
        Mosi        : IN    STD_LOGIC;-- := '0';
    
        Data1       : out   std_logic_vector(d_width-1 downto 0);-- := (others => '0');
        Data2       : out   std_logic_vector(d_width-1 downto 0);-- := (others => '0');

        Strob       : out std_logic--:='0'
    );
END spi_slave;

ARCHITECTURE logic OF spi_slave IS
  signal buff    : STD_LOGIC_vector(d_width-1 downto 0) := (others => '0');
  --signal buff2    : STD_LOGIC_vector(d_width-1 downto 0) := (others => '0');

  signal buff_r0    : STD_LOGIC_vector(d_width-1 downto 0) := (others => '0');
  signal buff_r1    : STD_LOGIC_vector(d_width-1 downto 0) := (others => '0');
  signal bit_counter : std_logic_vector (d_width downto 0) := (others => '0');
  signal strob_counter : std_logic_vector (d_width downto 0) := (others => '0');
  
  signal ss : std_logic;
  signal clock : std_logic;
  signal stb : std_logic  := '0';

  signal strob_start : std_logic := '0';
  signal strob_stop : std_logic:= '0';

BEGIN
  
  ss <= Shift;
  clock <= Clk;

  process(ss,clock)
  begin
    if(rising_edge(ss)) then
        bit_counter <= (others => '0');
        strob_start <= '0';
        elsif(falling_edge(clock) and ss = '1') THEN
            IF(bit_counter = d_width) THEN
                case(buff(1)) is
                    when '0' => buff_r0 <= buff;
                    when '1' => buff_r1 <= buff;
                    when others => null;
                    end case;
                    strob_start <= '1';

                else
                    buff <= Mosi & buff(d_width-1 downto 1);
                    bit_counter <= bit_counter + 1;
            end if;

        end if;
    
    
    if(falling_edge(ss)) then
        strob_counter <= (others => '0');
        
        elsif(falling_edge(clock) and stb = '1') then
        if(strob_counter = 1) then
            strob_stop <= '1';
            else strob_counter <= strob_counter + 1;
        end if;
    end if;
    END PROCESS;

    Data1 <= buff_r0;
  Data2 <= buff_r1;

  stb <= strob_start and (not strob_stop);

  Strob <= stb;
END logic;

-- spi_TB.vhd

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity testbench is
  GENERIC(
    d_width : INTEGER := 12);
end testbench;

architecture SPI_test of testbench is

    
    component spi_slave is
    port
    (
        Clk         : IN    STD_LOGIC;  --spi clk from master
        Shift          : IN    STD_LOGIC;  --active low slave select
        Mosi        : IN    STD_LOGIC;

        Data1        : out   std_logic_vector(d_width-1 downto 0) := (others => '0');
        Data2        : out   std_logic_vector(d_width-1 downto 0) := (others => '0');
        Strob       : out std_logic:='0'
    );
    end component;

     signal kod : std_logic_vector( 11 DOWNTO 0 ) := "101100010110";

    signal clock    : std_logic := '0';
    signal clk_in   : std_logic;
    signal data1_out : std_logic_vector( d_width-1 DOWNTO 0 );
    signal data2_out : std_logic_vector( d_width-1 DOWNTO 0 );
    signal start    : std_logic  := '0';
    signal stop    : std_logic  := '0';

    signal mosi_tb     : std_logic;

    signal counter : std_logic_vector( d_width DOWNTO 0 );-- := (others => '0');
    signal ss : std_logic;

    signal strb : std_logic  := '0';

begin
    start <= '1' after 110 ns;
    
    clk : PROCESS(clock)
    BEGIN
        IF clock = '1' THEN
              clock <= '0' after 25 ns;
          ELSIF true THEN
              clock <= '1' after 25 ns;
          END IF;
        clk_in <=  clock;
    END PROCESS;

    data : PROCESS(clk_in, start)
    BEGIN
        if(rising_edge(start)) then
            counter <= (others => '0');
        
        elsif(falling_edge(clk_in) and counter = d_width) then
            --counter <= (others => '0');
            stop <= '1';

            elsif(falling_edge(clk_in) and ss = '1') THEN
                mosi_tb <= kod(0);
                counter <= counter + 1;
                kod <= '0' & kod(d_width-1 downto 1);
        end if;
    END PROCESS;

    ss <= start and (not stop);
    
    spi_slave_0 : spi_slave
    port map
    (
        Clk => clk_in,
        Shift => ss,
        Mosi => mosi_tb,
        Data1 => data1_out,
        Data2 => data2_out,
        Strob => strb
    );
end SPI_test;