typedef struct {
  __IO uint8_t A;
  __IO uint8_t B;
  uint16_t RES;
} DEV_t;

  DEV_t Dev;
  DEV_t *pDev = &Dev;

  pDev->A = 0x55;
  pDev->B = 0xAA;
  (uint16_t)pDev->A = 0x3333;
  (uint32_t)pDev->A = 0x01234567;

typedef struct {
  __I uint8_t RCR;    //<! Revision Code Register,            0x00
  __I uint8_t DBSR;    //<! Dislpay Buffer Size Register,        0x01
  __I uint8_t CRR;    //<! Configuration Readback Register,        0x02
} ReadOnlyConf_t;    //<! Read-Only Configuration Registers

typedef struct {
  __IO uint8_t MCCR;    //<! Memory Clock Configuration Register,    0x04
  __IO uint8_t PCCR;    //<! Pixel Clock Configuration Register,    0x05
} ClockConf_t;        //<! Clock Configuration Registers
...

#define DPYCTRL_BASE    ((uint32_t)0x6C000000)    //<! Dysplay base address
#define S1DREGS_BASE    DPYCTRL_BASE        //<! S1D13706 registers base

#define READONLYCONF_BASE    S1DREGS_BASE
#define CLOCKCONF_BASE        S1DREGS_BASE + 0x04
#define LOOKUPTABLE_BASE    S1DREGS_BASE + 0x08
...
#define READONLYCONF    ((ReadOnlyConf_t *) READONLYCONF_BASE)
#define CLOCKCONF    ((ClockConf_t *) CLOCKCONF_BASE)
#define LOOKUPTABLE    ((LookUpTable_t *) LOKUPTABLE_BASE)
...

typedef struct
{
  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
  union
{
  __IO uint8_t  reg8bit;        /*!< CRC Independent data register, Address offset: 0x04 */
  uint32_t IDR_space;
} IDR;
  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
} CRC_TypeDef;

typedef struct
{
  uint32_t DR;
  uint8_t  IDR;
  uint8_t  spacer;
  uint16_t  spacer2;
  uint32_t CR;
} CRCpeDef;

...
  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
  // __IO uint32_t BSRR;        // GPIO port bit set/reset: 0xRRRRSSSS, Address offset: 0x18
...
} GPIO_TypeDef;

#define        FX2_FIFO2            (*(volatile unsigned int *)(FX2_BASE_ADDR + (0x00UL<<2)))
#define        FX2_FIFO4            (*(volatile unsigned int *)(FX2_BASE_ADDR + (0x02UL<<2)))

Inline void pin_set_by_msk(const GPIO_typedef *port, const uint16_t msk, const bool state)
{
  port->BSRR = state?(msk):(msk<<16);
}