create_generated_clock -name ssram_clk_pin -source $ssram_clk_phy [get_ports {SSRAM_CLK}]


set tAC 3.4
set tOH 1.3

set tCM_Hold -0.4
set tCM_Setup 1.4

set tD_Hold -0.4
set tD_Setup 1.4

set tA_Hold -0.4
set tA_Setup 1.4
                                    
set_input_delay -clock [get_clocks {ssram_clk_pin}] -max $tAC [get_ports {SSRAM_DQ[*]}]
set_input_delay -clock [get_clocks {ssram_clk_pin}] -min $tOH [get_ports {SSRAM_DQ[*]}] -add_delay

set_output_delay -clock [get_clocks {ssram_clk_pin}] -max $tD_Setup [get_ports {SSRAM_DQ[*]}]
set_output_delay -clock [get_clocks {ssram_clk_pin}] -min $tD_Hold [get_ports {SSRAM_DQ[*]}] -add_delay

set_output_delay -clock [get_clocks {ssram_clk_pin}] -max $tA_Setup [get_ports {SSRAM_A[*]}]
set_output_delay -clock [get_clocks {ssram_clk_pin}] -min $tA_Hold [get_ports {SSRAM_A[*]}] -add_delay

set_output_delay -clock [get_clocks {ssram_clk_pin}] -max $tCM_Setup [get_ports {SSRAM_OEn}]
set_output_delay -clock [get_clocks {ssram_clk_pin}] -min $tCM_Hold [get_ports {SSRAM_OEn}] -add_delay

set_output_delay -clock [get_clocks {ssram_clk_pin}] -max $tCM_Setup [get_ports {SSRAM_CE1n}]
set_output_delay -clock [get_clocks {ssram_clk_pin}] -min $tCM_Hold [get_ports {SSRAM_CE1n}] -add_delay

set_output_delay -clock [get_clocks {ssram_clk_pin}] -max $tCM_Setup [get_ports {SSRAM_BWEn}]
set_output_delay -clock [get_clocks {ssram_clk_pin}] -min $tCM_Hold [get_ports {SSRAM_BWEn}] -add_delay

set_output_delay -clock [get_clocks {ssram_clk_pin}] -max $tCM_Setup [get_ports {SSRAM_ADSPn}]
set_output_delay -clock [get_clocks {ssram_clk_pin}] -min $tCM_Hold [get_ports {SSRAM_ADSPn}] -add_delay

SSRAM_DQ[14] - qsys1:qsys1_inst|altera_avalon_mm_clock_crossing_bridge:mm_clock_crossing_bridge_1|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0|altsyncram_60d1:auto_generated|ram_block1a0~porta_datain_reg0

SSRAM_DQ[14] - sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[31]

....................