logic cnt_rst;
logic cnt_rst2;

logic [63:0] cnt_41;
logic [63:0] cnt_156;
logic [63:0] cnt_41_back;

logic [63:0] cnt_156_sync_d1;
logic [63:0] cnt_41_back_sync_d1;

//главный счетчик
always_ff @( posedge clk_41m667 )
begin
if( cnt_rst )
cnt_41 <= '0;
else
cnt_41 <= cnt_41 + 1'd1;
end

always_ff @( posedge clk_156m25 )
begin
if( cnt_rst2 )
cnt_156_sync_d1 <= '0;
else
cnt_156_sync_d1 <= cnt_41;
end

always_ff @( posedge clk_156m25 )
begin
if( cnt_rst2 )
cnt_156 <= '0;
else
cnt_156 <= cnt_156_sync_d1;
end

//перебрасываем обратно на 41.667
always_ff @( posedge clk_41m667 )
begin
if( cnt_rst )
cnt_41_back_sync_d1 <= '0;
else
cnt_41_back_sync_d1 <= cnt_156;
end

always_ff @( posedge clk_41m667 )
begin
if( cnt_rst )
cnt_41_back <= '0;
else
cnt_41_back <= cnt_41_back_sync_d1;
end

logic [63:0] diff;
logic [63:0] max_diff;

logic [63:0] cnt_41_save;
logic [63:0] cnt_41_back_save;

logic [63:0] diff_buf;

always_comb
begin
if(cnt_41_back > cnt_41)
diff = cnt_41_back - cnt_41;
else
diff = cnt_41 - cnt_41_back;
end

always_ff @( posedge clk_41m667 )
begin
if( cnt_rst )
begin
max_diff <= '0;
cnt_41_save <= '0;
cnt_41_back_save <= '0;
end
else
if( ( diff >= max_diff ) && ( cnt_41_back > 10 ) )
begin
max_diff <= diff;
cnt_41_save <= cnt_41;
cnt_41_back_save <= cnt_41_back;
end
end

logic [63:0] cnt, reg_other, reg_back, err_cnt, diff;
logic err;
always @(posedge clk2) begin
  cnt <= cnt+1'b1;
  reg_back <= reg_other;
  diff <= cnt - reg_back;
  err <= diff > 10;
  err_cnt <= err_cnt + err;
end
always @(posedge clk1)  reg_other <= cnt;

always_ff @( posedge clk_156m25 )
begin
if( cnt_rst2 )
cnt_156_sync_d1 <= '0;
else
cnt_156_sync_d1 <= cnt_41;
end

always_ff @( posedge clk_156m25 )
begin
if( cnt_rst2 )
cnt_156 <= '0;
else
cnt_156 <= cnt_156_sync_d1;
end