set main_clk u1|altpll_component|auto_generated|pll1|clk[0]
set sdram_clk u1|altpll_component|auto_generated|pll1|clk[1]
create_generated_clock -name sdram_clk_pin -source $sdram_clk
set_clock_groups -exclusive -group [list $main_clk $sdram_clk sdram_clk_pin]
#**************************************************************
# sdram timings
#**************************************************************
set tAC 5.4
set tOH 3
set tCM_Hold 0.8
set tCM_Setup 1.5
set tD_Hold 0.8
set tD_Setup 1.5
set tA_Hold 0.8
set tA_Setup 1.5
set_input_delay -max -clock sdram_clk_pin $tAC [get_ports {sdram_dq[*]}]
set_input_delay -min -clock sdram_clk_pin $tOH [get_ports {sdram_dq[*]}]
set_output_delay -max -clock sdram_clk_pin $tD_Setup [get_ports {sdram_dq[*]}]
set_output_delay -min -clock sdram_clk_pin $tD_Hold [get_ports {sdram_dq[*]}]
set_output_delay -max -clock sdram_clk_pin $tCM_Setup [get_ports {sdram_cas_n sdram_ras_n sdram_we_n sdram_cs_n sdram_cke sdram_dqm[*]}]
set_output_delay -min -clock sdram_clk_pin $tCM_Hold [get_ports {sdram_cas_n sdram_ras_n sdram_we_n sdram_cs_n sdram_cke sdram_dqm[*]}]
set_output_delay -max -clock sdram_clk_pin $tA_Setup [get_ports {sdram_addr[*] sdram_ba[*]}]
set_output_delay -min -clock sdram_clk_pin $tA_Hold [get_ports {sdram_addr[*] sdram_ba[*]}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks {sdram_clk_pin}] -to [get_clocks $main_clk] -setup -end 2
set_multicycle_path -from [get_clocks {sdram_clk_pin}] -to [get_clocks $main_clk] -hold -end 0