library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- Definition of Ports
-- FSL_Clk         : Synchronous clock
-- FSL_Rst         : System reset, should always come from FSL bus
-- FSL_S_Clk       : Slave asynchronous clock
-- FSL_S_Read      : Read signal, requiring next available input to be read
-- FSL_S_Data      : Input data
-- FSL_S_CONTROL   : Control Bit, indicating the input data are control word
-- FSL_S_Exists    : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk       : Master asynchronous clock
-- FSL_M_Write     : Write signal, enabling writing to output FSL bus
-- FSL_M_Data      : Output data
-- FSL_M_Control   : Control Bit, indicating the output data are contol word
-- FSL_M_Full      : Full Bit, indicating output FSL bus is full
-----------------------------------------------------------------------------
entity fsbox is
    port(
    --- global -----------------------------
        FSL_Clk         : in    std_logic;
        FSL_Rst         : in    std_logic;
        clk           : in    std_logic;
    --- io ---------------------------------
        input_data_r  : in    std_logic_vector(17 downto 0);
        input_data_i  : in    std_logic_vector(17 downto 0);
        output_data   : out    std_logic_vector(17 downto 0);
        tr_enbl       : out    std_logic;
    --- slave ------------------------------
        FSL_S_Clk      : in    std_logic;
        FSL_S_Read      : out    std_logic;
        FSL_S_Data      : in    std_logic_vector(0 to 31);
        FSL_S_Control : in    std_logic;
        FSL_S_Exists  : in    std_logic;
    --- master -----------------------------
        FSL_M_Clk      : in    std_logic;
        FSL_M_Write      : out    std_logic;
        FSL_M_Data      : out    std_logic_vector(0 to 31);
        FSL_M_Control : out    std_logic;
        FSL_M_Full      : in    std_logic
    );
    attribute SIGIS : string;
    attribute SIGIS of FSL_Clk : signal is "Clk";
    attribute SIGIS of FSL_S_Clk : signal is "Clk";
    attribute SIGIS of FSL_M_Clk : signal is "Clk";
    attribute iob: string;
end fsbox;

architecture EXAMPLE of fsbox is
---------------------------------------------------------------------------------
    signal sign18_data_in_r      : std_logic_vector(17 downto 0):=(others=>'0');
    signal sign18_data_in_i      : std_logic_vector(17 downto 0):=(others=>'0');
    signal sign18_data_out_ff_r  : std_logic_vector(17 downto 0):=(others=>'0');
    signal sign18_data_out_ff_i  : std_logic_vector(17 downto 0):=(others=>'0');
    signal sign18_data_out_fsl_r : std_logic_vector(0 to 31):=(others=>'0');
    signal sign18_data_out_fsl_i : std_logic_vector(0 to 31):=(others=>'0');
    signal full                  : std_logic:='0';
    signal empty                 : std_logic:='0';
    signal rd_en                 : std_logic:='0';
    signal i                     : integer:=0;
---------------------------------------------------------------------------------
    COMPONENT ififo  
        PORT (
            wr_clk : IN STD_LOGIC;
            rd_clk : IN STD_LOGIC;
            din    : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
            wr_en  : IN STD_LOGIC;
            rd_en  : IN STD_LOGIC;
            dout   : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
            full   : OUT STD_LOGIC;
            empty  : OUT STD_LOGIC
        );
    END COMPONENT;
begin
    input_ff_r : ififo PORT MAP(clk,FSL_Clk, input_data_r, '1', rd_en,sign18_data_out_ff_r,full,empty);
    input_ff_i : ififo PORT MAP(clk,FSL_Clk, input_data_i, '1', rd_en,sign18_data_out_ff_i,open, open);
---------------------------------------------------------------------------------------------
    Dout_IOB_Arr: for i in 17 downto 0
    generate
        attribute iob of Dout_IOB_r    : label is "TRUE";
        attribute iob of Dout_IOB_i    : label is "TRUE";
    begin
        Dout_IOB_r:  FD port map(D => input_data_r(i),Q => sign18_data_in_r(i), C => clk );
        Dout_IOB_i:  FD port map(D => input_data_i(i),Q => sign18_data_in_i(i), C => clk );
  end generate;
---------------------------------------------------------------------------------------------
    tr_enbl <= '0';
    sign18_data_out_fsl_i <= FSL_S_Data;
   output_data <= sign18_data_out_fsl_i(0 to 17);
    FSL_S_Read    <= '0';
---------------------------------------------------------------------------------------------
    wrt_data : process (FSL_Clk)
   begin  
        if FSL_Clk'event and FSL_Clk = '1' then
            if FSL_M_Full = '0' and empty = '0' then
                case i is
                    when 0 =>
                        rd_en <= '1';
                        i<=i+1;
                    when 1 =>
                        FSL_M_Write <= '1';
                        FSL_M_Control <= '1';
                        rd_en <= '1';
                        FSL_M_Data <= SXT(sign18_data_in_r, 32);
                        i<=i+1;
                    when 2 =>
                        FSL_M_Write <= '0';
                        FSL_M_Control <= '0';
                        rd_en <= '0';
                        i<=0;
                    when others =>
                end case;
            else
                FSL_M_Write <= '0';
                rd_en <= '0';
            end if;
        end if;
   end process wrt_data;
end architecture EXAMPLE;

    
        int h=0,g=0;
    delay(10);
    while (h<50){
        //getfsl(g,0);
        microblaze_nbread_cntlfsl(g,0);
        //nputfsl(g,0);
        xil_printf("%d;\n",g);
        h++;
    }