module Gen #(
    parameter N=15
)
(
    output G
);

wire [N-1:0] wi /* synthesis syn_keep=1 */;
assign G=wi[N-1];

genvar ii;
generate
    for (ii=0;ii<N;ii++) begin:gen
        //rtl version
        assign wi[ii==(N-1) ? 0 : ii+1]=!wi[ii];
/*        
        //primitive version (example for Xilinx LUT)        
        LUT1 #(
            .INIT(2'b01) // 0->1, 1->0
        )
        LUT1_i (
            .O (wi[ii==(N-1) ? 0: ii+1] ), // LUT output
            .I0(wi[ii]                  )  // LUT input
        );
*/        
    end

endgenerate
endmodule