ADI_EBIU_COMMAND_PAIR ezkit_ram[] = {
{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE, (void*)&bank_size },
{ ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank_width },
{ ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD, (void*)cl_threshold },
{ ADI_EBIU_CMD_SET_SDRAM_TRASMIN, (void*)&trasmin },
{ ADI_EBIU_CMD_SET_SDRAM_TRPMIN, (void*)&trpmin },
{ ADI_EBIU_CMD_SET_SDRAM_TRCDMIN, (void*)&trcdmin },
{ ADI_EBIU_CMD_SET_SDRAM_TWRMIN, (void*)&twrmin },
{ ADI_EBIU_CMD_SET_SDRAM_REFRESH, (void*)&refresh },
/* Asynch Commands memory controller commands */
{ ADI_EBIU_CMD_SET_ASYNCH_CLKOUT_ENABLE, (void*)&clkout_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ENABLE, (void*)&banks_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_TRANSITION_TIME, (void*)&asynch_bank_trans_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_ACCESS_TIME, (void*)&asynch_bank_read_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_ACCESS_TIME, (void*)&asynch_bank_write_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_SETUP_TIME, (void*)&asynch_bank_setup_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_HOLD_TIME, (void*)&asynch_bank_hold_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_ENABLE, (void*)&asynch_bank_ardy_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_POLARITY, (void*)&asynch_bank_ardy_polarity },
{ ADI_EBIU_CMD_END, 0 }
};