ERROR:Place:1205 - This design contains a global buffer instance, <DSP_CLKBUF>, driving the net, <Clk48MOut_OBUF>, that is driving the following (first 30) non-clock load pins off chip. This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net.

    DCM_CLKGEN_inst4 : DCM_CLKGEN
    generic map
    (
        CLKFXDV_DIVIDE  => 2,       -- CLKFXDV divide value (2, 4, 8, 16, 32)
        CLKFX_DIVIDE    => 27,      -- Divide value - D - (1-256)
        CLKFX_MD_MAX    => 0.0,     -- Specify maximum M/D ratio for timing anlysis
        CLKFX_MULTIPLY  => 50,      -- Multiply value - M - (2-256)
        CLKIN_PERIOD    => 37.0,    -- Input clock period specified in nS
        SPREAD_SPECTRUM => "NONE",  -- Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
                                    -- "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2"
        STARTUP_WAIT    => FALSE    -- Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
    )
    port map
    (
        CLKFX       => clk_DCM4p,   -- 1-bit output: Generated clock output
        CLKFX180    => clk_DCM4n,   -- 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
        CLKFXDV     => open,        -- 1-bit output: Divided clock output
        LOCKED      => open,        -- 1-bit output: Locked output
        PROGDONE    => open,        -- 1-bit output: Active high output to indicate the successful re-programming
        STATUS      => open,        -- 2-bit output: DCM_CLKGEN status
        CLKIN       => clk_27MHz,   -- 1-bit input: Input clock
        FREEZEDCM   => '0',         -- 1-bit input: Prevents frequency adjustments to input clock
        PROGCLK     => '0',         -- 1-bit input: Clock input for M/D reconfiguration
        PROGDATA    => '0',         -- 1-bit input: Serial data input for M/D reconfiguration
        PROGEN      => '0',         -- 1-bit input: Active high program enable
        RST         => '0'          -- 1-bit input: Reset input pin
    );

    ODDR2_inst4: ODDR2
    generic map
    (
        DDR_ALIGNMENT   => "NONE",  -- Sets output alignment to "NONE", "C0", "C1"
        INIT            => '0',     -- Sets initial state of the Q output to '0' or '1'
        SRTYPE          => "SYNC"   -- Specifies "SYNC" or "ASYNC" set/reset
    )
    port map
    (
        Q  => clk4,         -- 1-bit output data
        C0 => clk_DCM4p,    -- 1-bit clock input
        C1 => clk_DCM4n,    -- 1-bit clock input
        CE => '1',          -- 1-bit clock enable input
        D0 => '1',          -- 1-bit data input (associated with C0)
        D1 => '0',          -- 1-bit data input (associated with C1)
        R  => '0',          -- 1-bit reset input
        S  => '0'           -- 1-bit set input
    );

    -----------------------------------------------------------------------------------------------
    -----------------------------------------------------------------------------------------------


    PLL_BASE_inst : PLL_BASE
    generic map
    (
        BANDWIDTH => "OPTIMIZED",   -- "HIGH", "LOW" or "OPTIMIZED"
        CLKFBOUT_MULT   => 2,       -- Multiply value for all CLKOUT clock outputs (1-64)
        CLKFBOUT_PHASE  => 0.0,     -- Phase offset in degrees of the clock feedback output (0.0-360.0).
        CLKIN_PERIOD    => 20.0,    -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
        -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
        CLKOUT0_DIVIDE => 1,
        CLKOUT1_DIVIDE => 1,
        CLKOUT2_DIVIDE => 1,
        CLKOUT3_DIVIDE => 1,
        CLKOUT4_DIVIDE => 1,
        CLKOUT5_DIVIDE => 1,
        -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
        CLKOUT0_DUTY_CYCLE => 0.5,
        CLKOUT1_DUTY_CYCLE => 0.5,
        CLKOUT2_DUTY_CYCLE => 0.5,
        CLKOUT3_DUTY_CYCLE => 0.5,
        CLKOUT4_DUTY_CYCLE => 0.5,
        CLKOUT5_DUTY_CYCLE => 0.5,
        -- CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
        CLKOUT0_PHASE => 0.0,
        CLKOUT1_PHASE => 45.0,
        CLKOUT2_PHASE => 90.0,
        CLKOUT3_PHASE => 180.0,
        CLKOUT4_PHASE => 0.0,
        CLKOUT5_PHASE => 0.0,
        CLK_FEEDBACK => "CLKFBOUT",           -- Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
        COMPENSATION => "SYSTEM_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
        DIVCLK_DIVIDE => 1,                   -- Division value for all output clocks (1-52)
        REF_JITTER => 0.1,                    -- Reference Clock Jitter in UI (0.000-0.999).
        RESET_ON_LOSS_OF_LOCK => FALSE        -- Must be set to FALSE
    )
    port map
    (
        CLKFBOUT    => pll_fb,      -- 1-bit output: PLL_BASE feedback output
        CLKOUT0     => pll_clkout,
        CLKOUT1     => open,
        CLKOUT2     => open,
        CLKOUT3     => open,
        CLKOUT4     => open,
        CLKOUT5     => open,
        LOCKED      => open,        -- 1-bit output: PLL_BASE lock status output
        CLKFBIN     => pll_fb,      -- 1-bit input: Feedback clock input
        CLKIN       => clk_DCM4p,   -- 1-bit input: Clock input
        RST         => '0'          -- 1-bit input: Reset input
    );

-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

ENTITY DCM_Block IS
PORT(
-- input clocks
SYSCLK20M : IN std_logic; -- input 20MHz clock

-- output clocks
Clk48M : OUT std_logic; -- 48MHz output system and dsp clock
Clk24M : OUT std_logic; -- 24MHz output holt clock
Clk08M : OUT std_logic; -- 08MHz output system clock

Inp48MLatch : IN std_logic;
Out48MLatch : OUT std_logic;

Inp08MLatch : IN std_logic;
Out08MLatch : OUT std_logic);

END DCM_Block;

ARCHITECTURE DCM_Block_Arch OF DCM_Block IS

-- clock buffer prototype - recommended
COMPONENT BUFG
PORT(
I : IN std_logic;
O : OUT std_logic );
END COMPONENT;

-- ODDR2 component

COMPONENT ODDR2
GENERIC(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC" );
PORT(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic := 'H';
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L' );
END COMPONENT;


-- PLL COMPONENT

COMPONENT PLL_BASE
GENERIC(
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 24;
CLKFBOUT_PHASE : real := 0.0;
CLKIN_PERIOD : real := 50.000000;

CLKOUT0_DIVIDE : integer := 10;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 90.0;
CLKOUT1_DIVIDE : integer := 10;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 270.0;

CLKOUT2_DIVIDE : integer := 20;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 90.0;
CLKOUT3_DIVIDE : integer := 20;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 270.0;

CLKOUT4_DIVIDE : integer := 60;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 90.0;
CLKOUT5_DIVIDE : integer := 60;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 270.0;

CLK_FEEDBACK : string := "CLKFBOUT";
COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER : real := 0.100;
RESET_ON_LOSS_OF_LOCK : boolean := FALSE );
PORT(
CLKFBOUT : out std_ulogic;
CLKOUT0 : out std_ulogic;
CLKOUT1 : out std_ulogic;
CLKOUT2 : out std_ulogic;
CLKOUT3 : out std_ulogic;
CLKOUT4 : out std_ulogic;
CLKOUT5 : out std_ulogic;
LOCKED : out std_ulogic;
CLKFBIN : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic );
END COMPONENT;

-- to avaod waring
attribute box_type of PLL_BASE : component is "black_box";
attribute box_type of BUFG : component is "black_box";
attribute box_type of ODDR2 : component is "black_box";

-- Signal Declarations:
signal Reset_PLL : std_logic; -- DCM reset

-- FSM

-- Watchdog signals
constant DcmReset : integer := 7;

-- clock generation signals
signal PllFeedBack : std_logic; -- pll lock signal
signal PllLocked : std_logic; -- pll lock signal

signal SYSCLK20M_B : std_logic; -- pll lock signal

signal PLL_48_Dir : std_logic; -- from pll to bufg
signal PLL_48_Inv : std_logic; -- from pll to bufg
signal BUFG_48_Dir : std_logic; -- from bufg to oddr2
signal BUFG_48_Inv : std_logic; -- from bufg to oddr2
signal Clk48Out : std_logic; -- output 48MHz;

signal PLL_24_Dir : std_logic; -- from pll to bufg
signal PLL_24_Inv : std_logic; -- from pll to bufg
signal BUFG_24_Dir : std_logic; -- from bufg to oddr2
signal BUFG_24_Inv : std_logic; -- from bufg to oddr2
signal Clk24Out : std_logic; -- output 24MHz;

signal PLL_08_Dir : std_logic; -- from pll to bufg
signal PLL_08_Inv : std_logic; -- from pll to bufg
signal BUFG_08_Dir : std_logic; -- from bufg to oddr2
signal BUFG_08_Inv : std_logic; -- from bufg to oddr2
signal Clk08Out : std_logic; -- output 24MHz;

BEGIN
-- generating DCM reset signal
PLL_Reset : PROCESS( SYSCLK20M )
variable ResetClockCnt : integer range 0 to DcmReset := 0;
BEGIN
IF SYSCLK20M'event and SYSCLK20M = '1' THEN
IF ResetClockCnt < DcmReset THEN
Reset_PLL <= '1';
ResetClockCnt := ResetClockCnt + 1;
ELSE
Reset_PLL <= '0';
END IF;
END IF; -- ClkInp'event
END PROCESS PLL_Reset;

SYSCLK_BUFG : BUFG
PORT MAP (
I => SYSCLK20M,
O => SYSCLK20M_B );

-- Clock Generator
U_PLL_BASE : PLL_BASE
PORT MAP(
CLKFBOUT => PllFeedBack,
CLKOUT0 => PLL_48_Dir,
CLKOUT1 => PLL_48_Inv,
CLKOUT2 => PLL_24_Dir,
CLKOUT3 => PLL_24_Inv,
CLKOUT4 => PLL_08_Dir,
CLKOUT5 => PLL_08_Inv,
LOCKED => PllLocked,
CLKFBIN => PllFeedBack,
CLKIN => SYSCLK20M_B,
RST => Reset_PLL);

-- 48 MHz clock
CLK48M_DIR_CLKBUF : BUFG
PORT MAP (
I => PLL_48_Dir,
O => BUFG_48_Dir );

CLK48M_INV_CLKBUF : BUFG
PORT MAP (
I => PLL_48_Inv,
O => BUFG_48_Inv );

CLK48_ODDR2 : ODDR2
PORT MAP(
Q => Clk48Out,
C0 => BUFG_48_Dir,
C1 => BUFG_48_Inv,
D0 => '1',
D1 => '0',
S => '0',
R => '0',
CE => '1');

Clk48M <= Clk48Out;

-- 24 MHz clock
CLK24M_DIR_CLKBUF : BUFG
PORT MAP (
I => PLL_24_Dir,
O => BUFG_24_Dir );

CLK24M_INV_CLKBUF : BUFG
PORT MAP (
I => PLL_24_Inv,
O => BUFG_24_Inv );

CLK24_ODDR2 : ODDR2
PORT MAP(
Q => Clk24Out,
C0 => BUFG_24_Dir,
C1 => BUFG_24_Inv,
D0 => '1',
D1 => '0',
S => '0',
R => '0',
CE => '1');

Clk24M <= Clk24Out;

-- 8 MHz clock
CLK08M_DIR_CLKBUF : BUFG
PORT MAP (
I => PLL_08_Dir,
O => BUFG_08_Dir );

CLK08M_INV_CLKBUF : BUFG
PORT MAP (
I => PLL_08_Inv,
O => BUFG_08_Inv );

CLK08_ODDR2 : ODDR2
PORT MAP(
Q => Clk08Out,
C0 => BUFG_08_Dir,
C1 => BUFG_08_Inv,
D0 => '1',
D1 => '0',
S => '0',
R => '0',
CE => '1');

Clk08M <= Clk08Out;


LATCH08PRC : PROCESS(Clk08Out)
BEGIN
IF Clk08Out'event and Clk08Out = '1' THEN
Out08MLatch <= Inp08MLatch;
END IF;
END PROCESS LATCH08PRC;


LATCH48PRC : PROCESS(Clk48Out)
BEGIN
IF Clk48Out'event and Clk48Out = '1' THEN
Out48MLatch <= Inp48MLatch;
END IF;
END PROCESS LATCH48PRC;


END DCM_Block_Arch;

ERROR:Pack:2531 - The dual data rate register "CLK08_ODDR2" failed to join the
"OLOGIC2" component as required. The output signal for register symbol
CLK08_ODDR2 requires general routing to fabric, but the register can only be
routed to ILOGIC, IODELAY, and IOB.
ERROR:Pack:2531 - The dual data rate register "CLK48_ODDR2" failed to join the
"OLOGIC2" component as required. The output signal for register symbol
CLK48_ODDR2 requires general routing to fabric, but the register can only be
routed to ILOGIC, IODELAY, and IOB.

           +-> логика
PLL->BUFG->|
           +-> ODDR2->pin