ERROR:Place:1042 - Unroutable Placement! An IPAD / GT component pair have been
   found that are not placed at a routable IPAD / GT site pair. The IPAD
   component <plbv46_pcie_0_RXP_pin<1>> is placed at site <IPAD_X1Y9>. The
   corresponding GT component
   <plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i> is placed at site
   <GTX_DUAL_X0Y3>. The IPAD can route to the GT <RXP1> pin only if the load
   component is placed at an offset of (-2, -2) with respect to the driver
   component. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN "plbv46_pcie_0_RXP_pin_1_IBUF.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i.RXP1" CLOCK_DEDICATED_ROUTE =
   FALSE; >
ERROR:Place:1038 - Unroutable Placement! An IPAD / GT component pair have been
   found that are not placed at a routable IPAD / GT site pair. The IPAD
   component <plbv46_pcie_0_RXN_pin<1>> is placed at site <IPAD_X1Y8>. The
   corresponding GT component
   <plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i> is placed at site
   <GTX_DUAL_X0Y3>. The IPAD can route to the GT <RXN1> pin only if the load
   component is placed at an offset of (-2, -1) with respect to the driver
   component. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN "plbv46_pcie_0_RXN_pin_1_IBUF.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i.RXN1" CLOCK_DEDICATED_ROUTE =
   FALSE; >
ERROR:Place:1040 - Unroutable Placement! An IPAD / GT component pair have been
   found that are not placed at a routable IPAD / GT site pair. The IPAD
   component <plbv46_pcie_0_RXP_pin<0>> is placed at site <IPAD_X1Y7>. The
   corresponding GT component
   <plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i> is placed at site
   <GTX_DUAL_X0Y3>. The IPAD can route to the GT <RXP0> pin only if the load
   component is placed at an offset of (-2, -2) with respect to the driver
   component. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN "plbv46_pcie_0_RXP_pin_0_IBUF.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i.RXP0" CLOCK_DEDICATED_ROUTE =
   FALSE; >
ERROR:Place:1036 - Unroutable Placement! An IPAD / GT component pair have been
   found that are not placed at a routable IPAD / GT site pair. The IPAD
   component <plbv46_pcie_0_RXN_pin<0>> is placed at site <IPAD_X1Y6>. The
   corresponding GT component
   <plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i> is placed at site
   <GTX_DUAL_X0Y3>. The IPAD can route to the GT <RXN0> pin only if the load
   component is placed at an offset of (-2, 1) with respect to the driver
   component. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN "plbv46_pcie_0_RXN_pin_0_IBUF.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.co
   mp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep
   0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i.RXN0" CLOCK_DEDICATED_ROUTE =
   FALSE; >

Net plbv46_pcie_0_RXN_pin<0> LOC=T1;
Net plbv46_pcie_0_RXN_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXN_pin<1> LOC=U1;
Net plbv46_pcie_0_RXN_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXN_pin<2> LOC=K1;
Net plbv46_pcie_0_RXN_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXN_pin<3> LOC=L1;
Net plbv46_pcie_0_RXN_pin<3> IOSTANDARD = LVDS_25;

Net plbv46_pcie_0_RXP_pin<0> LOC=R1;
Net plbv46_pcie_0_RXP_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXP_pin<1> LOC=V1;
Net plbv46_pcie_0_RXP_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXP_pin<2> LOC=J1;
Net plbv46_pcie_0_RXP_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXP_pin<3> LOC=M1;
Net plbv46_pcie_0_RXP_pin<3> IOSTANDARD = LVDS_25;

Net plbv46_pcie_0_TXN_pin<0> LOC=C2;
Net plbv46_pcie_0_TXN_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXN_pin<1> LOC=F2;
Net plbv46_pcie_0_TXN_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXN_pin<2> LOC=J2;
Net plbv46_pcie_0_TXN_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXN_pin<3> LOC=M2;
Net plbv46_pcie_0_TXN_pin<3> IOSTANDARD = LVDS_25;

Net plbv46_pcie_0_TXP_pin<0> LOC=B2;
Net plbv46_pcie_0_TXP_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXP_pin<1> LOC=G2;
Net plbv46_pcie_0_TXP_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXP_pin<2> LOC=H2;
Net plbv46_pcie_0_TXP_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXP_pin<3> LOC=N2;
Net plbv46_pcie_0_TXP_pin<3> IOSTANDARD = LVDS_25;

#  Generic Template
Net fpga_0_Generic_GPIO_GPIO_IO_pin<0> LOC=E26;
Net fpga_0_Generic_GPIO_GPIO_IO_pin<1> LOC=E25;
Net fpga_0_Generic_GPIO_GPIO_IO_pin<2> LOC=F25;
Net fpga_0_Generic_GPIO_GPIO_IO_pin<3> LOC=G26;
Net fpga_0_Generic_GPIO_GPIO_IO_pin<4> LOC=G25;
Net fpga_0_Generic_GPIO_GPIO_IO_pin<5> LOC=H26;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 125000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC=AB14;
Net fpga_0_rst_1_sys_rst_pin TIG;
## Net fpga_0_rst_1_sys_rst_pin LOC=;

Net plbv46_pcie_0_RXN_pin<0> LOC=D1;
Net plbv46_pcie_0_RXN_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXN_pin<1> LOC=E1;
Net plbv46_pcie_0_RXN_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXN_pin<2> LOC=K1;
Net plbv46_pcie_0_RXN_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXN_pin<3> LOC=L1;
Net plbv46_pcie_0_RXN_pin<3> IOSTANDARD = LVDS_25;

Net plbv46_pcie_0_RXP_pin<0> LOC=C1;
Net plbv46_pcie_0_RXP_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXP_pin<1> LOC=F1;
Net plbv46_pcie_0_RXP_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXP_pin<2> LOC=J1;
Net plbv46_pcie_0_RXP_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_RXP_pin<3> LOC=M1;
Net plbv46_pcie_0_RXP_pin<3> IOSTANDARD = LVDS_25;

Net plbv46_pcie_0_TXN_pin<0> LOC=C2;
Net plbv46_pcie_0_TXN_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXN_pin<1> LOC=F2;
Net plbv46_pcie_0_TXN_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXN_pin<2> LOC=J2;
Net plbv46_pcie_0_TXN_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXN_pin<3> LOC=M2;
Net plbv46_pcie_0_TXN_pin<3> IOSTANDARD = LVDS_25;

Net plbv46_pcie_0_TXP_pin<0> LOC=B2;
Net plbv46_pcie_0_TXP_pin<0> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXP_pin<1> LOC=G2;
Net plbv46_pcie_0_TXP_pin<1> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXP_pin<2> LOC=H2;
Net plbv46_pcie_0_TXP_pin<2> IOSTANDARD = LVDS_25;
Net plbv46_pcie_0_TXP_pin<3> LOC=N2;
Net plbv46_pcie_0_TXP_pin<3> IOSTANDARD = LVDS_25;

Net util_ds_buf_0_IBUF_DS_N_pin  LOC=D3;
Net util_ds_buf_0_IBUF_DS_P_pin  LOC=D4;

PARAMETER VERSION = 2.1.0


PORT fpga_0_Generic_GPIO_GPIO_IO_pin = fpga_0_Generic_GPIO_GPIO_IO_pin_vslice_0_5_concat, DIR = IO, VEC = [0:5]
PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
PORT plbv46_pcie_0_RXN_pin = net_plbv46_pcie_0_RXN_pin, DIR = I, VEC = [3:0]
PORT plbv46_pcie_0_RXP_pin = net_plbv46_pcie_0_RXP_pin, DIR = I, VEC = [3:0]
PORT plbv46_pcie_0_TXN_pin = plbv46_pcie_0_TXN, DIR = O, VEC = [3:0]
PORT plbv46_pcie_0_TXP_pin = plbv46_pcie_0_TXP, DIR = O, VEC = [3:0]
PORT plbv46_pcie_0_REFCLK_pin = net_plbv46_pcie_0_REFCLK_pin, DIR = I
PORT util_ds_buf_0_IBUF_DS_N_pin = net_util_ds_buf_0_IBUF_DS_N_pin, DIR = I
PORT util_ds_buf_0_IBUF_DS_P_pin = net_util_ds_buf_0_IBUF_DS_P_pin, DIR = I


BEGIN ppc440_virtex5
PARAMETER INSTANCE = ppc440_0
PARAMETER C_IDCR_BASEADDR = 0b0000000000
PARAMETER C_IDCR_HIGHADDR = 0b0011111111
PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0
PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
PARAMETER HW_VER = 1.01.a
BUS_INTERFACE MPLB = plb_v46_0
BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
BUS_INTERFACE RESETPPC = ppc_reset_bus
BUS_INTERFACE SPLB0 = plb_v46_0
PORT CPMC440CLK = clk_200_0000MHzPLL0
PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0
PORT CPMINTERCONNECTCLKNTO1 = net_vcc
PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
PORT CPMMCCLK = clock_generator_0_CLKOUT0
PORT CPMC440TIMERCLOCK = clock_generator_0_CLKOUT0
PORT PPCEICINTERCONNECTIRQ = ppc440_0_PPCEICINTERCONNECTIRQ
END

BEGIN plbv46_pcie
PARAMETER INSTANCE = plbv46_pcie_0
PARAMETER HW_VER = 4.07.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000FFFF
PARAMETER C_IPIFBAR_0 = 0x00010000
PARAMETER C_IPIFBAR_HIGHADDR_0 = 0x0001FFFF
PARAMETER C_PCIBAR_LEN_0 = 16
PARAMETER C_NO_OF_LANES = 4
BUS_INTERFACE SPLB = plb_v46_0
BUS_INTERFACE MPLB = plb_v46_0
PORT Bridge_Clk = plbv46_pcie_0_Bridge_Clk
PORT RXN = net_plbv46_pcie_0_RXN_pin
PORT RXP = net_plbv46_pcie_0_RXP_pin
PORT TXN = plbv46_pcie_0_TXN
PORT TXP = plbv46_pcie_0_TXP
END

BEGIN util_ds_buf
PARAMETER INSTANCE = util_ds_buf_0
PARAMETER HW_VER = 1.01.a
PORT IBUF_DS_N = net_util_ds_buf_0_IBUF_DS_N_pin
PORT IBUF_DS_P = net_util_ds_buf_0_IBUF_DS_P_pin
PORT IBUF_OUT = util_ds_buf_0_IBUF_OUT
END

LIT:550 - CLKIN of GTX_DUAL symbol "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.comp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" (output signal=plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.comp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out<0>) is not driven by a BUFG, BUFR, IBUFDS, IBUFGDS or GT.
LIT:550 - CLKIN of GTX_DUAL symbol "plbv46_pcie_0/plbv46_pcie_0/gen_pcie_bridge_64.pcie_bridge_64/gen_v5_pcie.comp_block_plus/comp_v5_endpoint/endpoint_blk_plus_v1_13x4_i.ep_v1_13x4/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" is not driven by a BUFG, BUFR, IBUFDS, IBUFGDS or GT.