module videlyalka(input DATAIN, CLR, CLOCK, output DATAOUT);
   reg [4:0] sr1_q, sr2_q;
    reg fd1_q, fd2_q;
    wire clr1, clr2;
    
    assign clr11 = (|sr2_q) | CLR;
    
    always @(posedge CLOCK or posedge clr11)  begin    
       if(clr11) sr1_q <= 5'b0;
        else      sr1_q <= {sr1_q[3:0], DATAIN};    
   end
    
    assign clr12 = clr11 | sr1_q[4];
    
    always @(posedge CLOCK or posedge clr12)  begin    
       if(clr12) fd1_q <= 1'b0;    
        else      fd1_q <= DATAIN;    
   end
  
    assign clr21 = (|sr1_q) | CLR;

    always @(negedge CLOCK or posedge clr21)  begin    
       if(clr21) sr2_q <= 5'b0;
        else      sr2_q <= {sr2_q[3:0], DATAIN};    
   end

      assign clr22 = clr21 | sr2_q[4];

    always @(negedge CLOCK or posedge clr22)  begin    
       if(clr22) fd2_q <= 1'b0;    
        else      fd2_q <= DATAIN;    
   end
  
    assign DATAOUT = fd1_q | fd2_q;
endmodule