//----------- 2   3   4   5-е слово  -------------------------------------            
if ( reg_nomer_slova == 8'h02 | reg_nomer_slova == 8'h03 | reg_nomer_slova == 8'h04 | reg_nomer_slova == 8'h05)
  begin
casez (nomer_bit)
        5'b00???:   begin     //0..7                                 
            reg_CM_BC <=  (reg_nomer_slova == 8'h02) ?
                ( ( reg_kod_oper  == paket_znak ) ?  reg_kolich_znakov[nomer_bit]  :
                            ( ( reg_kod_oper  == paket_linia ) ?  reg_nach_koord_linii_Y[nomer_bit]  : 1'bz  ) ) :
                    (reg_nomer_slova == 8'h03) ?          
                        ( ( reg_kod_oper  == paket_znak ) ?  reg_koord_perv_znaka_Y[nomer_bit]  :  
                            ( ( reg_kod_oper  == paket_linia )  ?  reg_nach_koord_linii_X[nomer_bit]  : 1'bz  ) ) :
                        (reg_nomer_slova == 8'h04) ?        
                            ( ( reg_kod_oper  == paket_znak ) ?  reg_koord_perv_znaka_X[nomer_bit]  :  
                                ( ( reg_kod_oper  == paket_linia )  ?  reg_proekcii_linii_Y[nomer_bit]  : 1'bz  ) ) :        
                                ( ( reg_kod_oper  == paket_znak ) ?  reg_kod_znaka_bit_ml[nomer_bit]  :  
                                    ( ( reg_kod_oper  == paket_linia )  ?  reg_proekcii_linii_X[nomer_bit]  : 1'bz  ) );
                nomer_bit <= nomer_bit + 1'b1;    
            end
    5'b0100?:   begin     //8,9
            reg_podgotovki_smeni_slova <= 1'b0;
            reg_CM_BC <=  (reg_nomer_slova == 8'h02) ?
                        ( ( reg_kod_oper  == paket_znak ) ?  reg_kolich_znakov[nomer_bit]  :
                            ( ( reg_kod_oper  == paket_linia ) ?  reg_nach_koord_linii_Y[nomer_bit]  : 1'bz  ) ) :
                        (reg_nomer_slova == 8'h03) ?          
                            ( ( reg_kod_oper  == paket_znak ) ?  reg_koord_perv_znaka_Y[nomer_bit]  :  
                                ( ( reg_kod_oper  == paket_linia )  ?  reg_nach_koord_linii_X[nomer_bit]  : 1'bz  ) ) :
                            (reg_nomer_slova == 8'h04) ?        
                                ( ( reg_kod_oper  == paket_znak ) ?  reg_koord_perv_znaka_X[nomer_bit]  :  
                                ( ( reg_kod_oper  == paket_linia )  ?  reg_proekcii_linii_Y[nomer_bit]  : 1'bz  ) ):        
                                        ( ( reg_kod_oper  == paket_znak ) ?  reg_kod_znaka_bit_st[nomer_bit-8]  :  
                                    ( ( reg_kod_oper  == paket_linia )  ?  reg_proekcii_linii_X[nomer_bit]  : 1'bz  ) );
                    nomer_bit <= nomer_bit + 1'b1;    
                end                              
        5'b0101?:   begin     //10,11
        reg_CM_BC <=  (reg_nomer_slova == 8'h02 | reg_nomer_slova == 8'h03 | reg_nomer_slova == 8'h04) ?
                        ( ( reg_kod_oper  == paket_znak ) ?   1'b0  :
                            ( ( reg_kod_oper  == paket_linia ) ?   1'b0   : 1'bz  ) ) :
                                ( ( reg_kod_oper  == paket_znak ) ?  reg_kod_znaka_bit_st[nomer_bit-8]  :  
                                    ( ( reg_kod_oper  == paket_linia )  ?   1'b0  : 1'bz  ) );
                    nomer_bit <= nomer_bit + 1'b1;    
                end    
        5'b0110?:   begin      //12,13
            reg_CM_BC <=
                                       ...
                nomer_bit <= nomer_bit + 1'b1;    
            end    
        5'b01110:   begin      //14
            reg_CM_BC <=  ...

                nomer_bit <= nomer_bit + 1'b1;    
            end    
    5'b01111:   begin      //15
            reg_CM_BC <=
                                         ...
                nomer_bit <= nomer_bit + 1'b1;    
            end
    5'b10000:   begin      
                reg_CM_BC <=  1'b0;
                nomer_bit <= nomer_bit + 1'b1;    
             end          
    5'b10001:   begin
                reg_CM_BC <=  reg_kontr_razr;
                nomer_bit <= nomer_bit + 1'b1;                                
                            ...    
                                        
            end                          
                    default :   begin
                                
                                nomer_bit <= 5'b00000;
                                end      
        endcase
end    //reg_nomer_slova == 8'h02

always @(posedge clk_100_MHz )    
begin
    if( IZ_BC ==1 )
       reg_IZ_BC <= 1'b1;        
    else        
       reg_IZ_BC <= 1'b0;        
    if( CIB_BC ==1 )    
        reg_CIB_BC <= 1'b1;        
    else
        reg_CIB_BC <= 1'b0;        
    if( IZ_BC ==1 | CIB_BC ==1)            
        reg_IZ_BC_CIB_BC <= 1'b1;        
    else        
        reg_IZ_BC_CIB_BC <= 1'b0;                
end
always @( posedge reg_CIB_BC or posedge reg_IZ_BC  )    // reg_IZ_BC  в роли сброса
   begin    
    if ( reg_IZ_BC == 1 )
        begin
...
            end
       else
            begin
...
            end
  end

always @(  negedge reg_IZ_BC_CIB_BC )
begin    
  ...
   здесь приведенный ранее код
end

module synchronizer_CIB_BC (
    input clk,
    input reset,
    input din,
    output dout,
     output dout1
);
    reg d,dout,dout1;
    always @(posedge clk, posedge reset) begin
        if (reset) begin
            d <= 0;
            dout <= 0;
        dout1 <= 0;
        end
     else
        begin
            d <= din;
            dout <= d;
        dout1 <= dout;
        end
    end
endmodule

//===============  синхронизатор сброса   ==============
module async_reset (
input clk,
input reset_in,
output rst_out
);
reg rst_out, rff1;
always @(posedge clk or posedge reset_in)
if (reset_in)
    begin
        rst_out <= 1'b1;
        rff1  <= 1'b1;
    end
else
    begin
        rff1 <= 1'b0;
        rst_out <= rff1;
    end
endmodule

...
reg [7:0] reg_kod_znaka[61:0];
...
task paket_znak_3;
begin
    ...
    reg_kod_znaka[0] = 8'hf0;
    reg_kod_znaka[1] = 8'hf1;
    ...
    reg_kod_znaka[9] = 8'hf9;
...
end
endtask
always @(posedge clk_100_MHz )    
begin
...
paket_znak_3;
...
end