library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;

entity main is
GENERIC(
count_width : INTEGER := 8
);

Port ( clk_in : in STD_LOGIC;
f15_1 : in STD_LOGIC_VECTOR(4 DOWNTO 0);
fm1 : out STD_LOGIC);
end main;

architecture Behavioral of main is

signal count : STD_LOGIC_VECTOR(count_width-1 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, count_width);
signal temp_clk_out : STD_LOGIC := '0';

begin

p1: process(clk_in, count)
begin
if rising_edge(clk_in) then
if f15_1 = CONV_STD_LOGIC_VECTOR(0, 5) then
temp_clk_out <= clk_in;
else
if count /= (f15_1-1) then
count <= count + '1';
else
count <= CONV_STD_LOGIC_VECTOR(0, count_width);
end if;

if count = CONV_STD_LOGIC_VECTOR(1, count_width) then
temp_clk_out <= '1';
else
temp_clk_out <= '0';
end if;
end if;
end if;
end process;

fm1 <= temp_clk_out;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;

entity main is
GENERIC(
count_width : INTEGER := 8
);

Port ( clk_in : in STD_LOGIC;
wr_fm15_1 : in STD_LOGIC;
fm15_1 : in STD_LOGIC_VECTOR(4 DOWNTO 0);
fm1 : out STD_LOGIC);
end main;

architecture Behavioral of main is

signal count : STD_LOGIC_VECTOR(count_width-1 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, count_width);
signal temp_clk_out : STD_LOGIC := '0';
signal temp_fm15_1 : STD_LOGIC_VECTOR(4 DOWNTO 0);

begin

p1 : process(wr_fm15_1, count)
begin
if rising_edge(wr_fm15_1) then
temp_fm15_1(4 DOWNTO 0) <= '0' & fm15_1(4 downto 1);
end if;
end process;


p2 : process(clk_in, count)
begin
if rising_edge(clk_in) then
case conv_integer(temp_fm15_1) is
when 0 => temp_clk_out <= clk_in;
when 1 => temp_clk_out <= not temp_clk_out;
when others =>
if count /= (temp_fm15_1-1) then
count <= count + '1';
else
count <= CONV_STD_LOGIC_VECTOR(0, count_width);
end if;
END CASE;
if count = CONV_STD_LOGIC_VECTOR(1, count_width) then
temp_clk_out <= not temp_clk_out;
end if;
end if;
end process;

fm1 <= temp_clk_out;

end Behavioral;

frequancy8khz: process( f2_5) --частота f2_5 ранее сформированная частота из тактовой
variable f8k: integer range 0 to 19 := 0;
begin
IF clr ='1' THEN
f8k:=0;
ELSIF rising_edge( f2_5 ) THEN
IF f8k=0 THEN
f8k:=19;
else
f8k:=f8k-1;
end if;

IF f8k>9 THEN
freq8k<='1';

else
freq8k<='0';
end if;
end if;

end process;

f8k<=freq8k;

frequency15Hz_10: process (f8k)
variable f15_10: integer range 0 to 11 :=0;
BEGIN
if clr ='1' THEN
f15_10:=0;
ELSIF rising_edge( f8k ) THEN
if f15_10=0 THEN
f15_10:=11;
else
f15_10:=f15_10-1;

end if;

IF f15_10>6 THEN
freq15_10<='1';
else
freq15_10<='0';

end if;
end if;

END PROCESS;