.include "m1281def.inc"

jmp RESET ; Reset Handler
reti ;jmp INT0 ; IRQ0 Handler
reti ;jmp INT1 ; IRQ1 Handler
reti ;jmp INT2 ; IRQ2 Handler
reti ;jmp INT3 ; IRQ3 Handler
reti ;jmp INT4 ; IRQ4 Handler
reti ;jmp INT5 ; IRQ5 Handler
reti ;jmp INT6 ; IRQ6 Handler
reti ;jmp INT7 ; IRQ7 Handler
reti ;jmp PCINT0 ; PCINT0 Handler
reti ;jmp PCINT1 ; PCINT1 Handler
reti ;jmp PCINT2 ; PCINT2 Handler
reti ;jmp WDT ; Watchdog Timeout Handler
reti ;jmp TIM2_COMPA ; Timer2 CompareA Handler
reti ;jmp TIM2_COMPB ; Timer2 CompareB Handler
reti ;jmp TIM2_OVF ; Timer2 Overflow Handler
reti ;jmp TIM1_CAPT ; Timer1 Capture Handler
reti ;jmp TIM1_COMPA ; Timer1 CompareA Handler
reti ;jmp TIM1_COMPB ; Timer1 CompareB Handler
reti ;jmp TIM1_COMPC ; Timer1 CompareC Handler
reti ;jmp TIM1_OVF ; Timer1 Overflow Handler
reti ;jmp TIM0_COMPA ; Timer0 CompareA Handler
reti ;jmp TIM0_COMPB ; Timer0 CompareB Handler
reti ;jmp TIM0_OVF ; Timer0 Overflow Handler
reti ;jmp SPI_STC ; SPI Transfer Complete Handler
jmp USART0_RXC ; USART0 RX Complete Handler
jmp USART0_UDRE ; USART0,UDR Empty Handler
jmp USART0_TXC ; USART0 TX Complete Handler
reti ;jmp ANA_COMP ; Analog Comparator Handler
reti ;jmp ADC ; ADC Conversion Complete Handler
reti ;jmp EE_RDY ; EEPROM Ready Handler
reti ;jmp TIM3_CAPT ; Timer3 Capture Handler
reti ;jmp TIM3_COMPA ; Timer3 CompareA Handler
reti ;jmp TIM3_COMPB ; Timer3 CompareB Handler
reti ;jmp TIM3_COMPC ; Timer3 CompareC Handler
reti ;jmp TIM3_OVF ; Timer3 Overflow Handler
jmp USART1_RXC ; USART1 RX Complete Handler
jmp USART1_UDRE ; USART1,UDR Empty Handler
jmp USART1_TXC ; USART1 TX Complete Handler
reti ;jmp TWI ; 2-wire Serial Handler
reti ;jmp SPM_RDY ; SPM Ready Handler
reti;jmp TIM4_CAPT ; Timer4 Capture Handler
reti;jmp TIM4_COMPA ; Timer4 CompareA Handler
reti;jmp TIM4_COMPB ; Timer4 CompareB Handler
reti;jmp TIM4_COMPC ; Timer4 CompareC Handler
reti;jmp TIM4_OVF ; Timer4 Overflow Handler
reti;jmp TIM5_CAPT ; Timer5 Capture Handler
reti;jmp TIM5_COMPA ; Timer5 CompareA Handler
reti;jmp TIM5_COMPB ; Timer5 CompareB Handler
reti;jmp TIM5_COMPC ; Timer5 CompareC Handler
reti;jmp TIM5_OVF ; Timer5 Overflow Handler
reti;jmp USART2_RXC ; USART2 RX Complete Handler
reti;jmp USART2_UDRE ; USART2,UDR Empty Handler
reti;jmp USART2_TXC ; USART2 TX Complete Handler
reti;jmp USART3_RXC ; USART3 RX Complete Handler
reti;jmp USART3_UDRE ; USART3,UDR Empty Handler
reti;jmp USART3_TXC ; USART3 TX Complete Handler

RESET:
ldi R16, low(RAMEND) ; ??????? ????? ?????? RAMEND
out SPL, R16 ; ????????????? SPL
ldi R16, high(RAMEND) ; ??????? ????? ?????? RAMEND
out SPH, R16 ; ????????????? SPH

uart_init:


.equ XTAL = 8000000
.equ baudrate = 9600
.equ bauddivider = XTAL/(16*baudrate)-1
.equ addr= 11
.equ Command = 0x03


LDI R16, low(bauddivider)
STS UBRR0L,R16
LDI R16, high(bauddivider)
STS UBRR0H,R16
LDI R16,0
STS UCSR0A, R16
LDI R16, (1<<RXEN0)|(1<<TXEN0)|(1<<RXCIE0)|(1<<TXCIE0)|(0<<UDRIE0)
STS UCSR0B, R16
LDI R16, (1<<UCSZ00)|(1<<UCSZ01)|(0<<UCSZ02)
STS UCSR0C, R16

LDI R16, low(bauddivider)
STS UBRR1L,R16
LDI R16, high(bauddivider)
STS UBRR1H,R16
LDI R16,0
STS UCSR1A, R16
LDI R16, (1<<RXEN1)|(1<<TXEN1)|(1<<RXCIE1)|(1<<TXCIE1)|(0<<UDRIE1)
STS UCSR1B, R16
LDI R16, (1<<UCSZ10)|(1<<UCSZ11)|(0<<UCSZ12)
STS UCSR1C, R16
main1:












ldi R16,1
sts UDR0,R16
sei
main:
sei
sbi DDRB,7
sbi PORTB,7
nop
rjmp main

USART1_RXC: ; USART RX Complete Handler
nop
cli
sbi DDRB,0
sbi PORTB,0
ldi R16,1
sts UDR0,R16
ret
USART1_UDRE: ; UDR Empty Handler
cli
sbi DDRB,1
sbi PORTB,1
ldi R16,1
sts UDR0,R16
nop
ret
USART1_TXC:
cli
sbi DDRB,2
sbi PORTB,2
ldi R16,1
sts UDR0,R16
ret
nop



USART0_RXC:
cli
sbi DDRB,0
sbi PORTB,0
ldi R16,2
sts UDR0,R16
ret
USART0_UDRE: ; USART0,UDR Empty Handler
cli
sbi DDRB,1
sbi PORTB,1
ldi R16,2
sts UDR0,R16
nop
ret
USART0_TXC:
cli
sbi DDRB,2
sbi PORTB,2
ldi R16,2
sts UDR0,R16
ret
nop



USART2_RXC:
cli
sbi DDRB,0
sbi PORTB,0
ldi R16,3
sts UDR0,R16
ret
USART2_UDRE: ; USART0,UDR Empty Handler
cli
sbi DDRB,1
sbi PORTB,1
ldi R16,3
sts UDR0,R16
nop
ret
USART2_TXC:
cli
sbi DDRB,2
sbi PORTB,2
ldi R16,3
sts UDR0,R16
ret
nop