while (ETH_GetSoftwareResetStatus() == SET);

... init()
{
...
/* enable clocking of ports A, B, C, AFIO */
RCC_APB2ENR |= (1 << 4) /* IOPCEN */
| (1 << 3) /* IOPBEN */
| (1 << 2) /* IOPAEN */
| (1 << 0);/* AFIOEN */
AFIO_MAPR |= (1 << 23); /* select RMII mode */
/* enable clocking of MAC core */
RCC_AHBENR |= (1 << 16) /* ETHMACRXEN */
| (1 << 15) /* ETHMACTXEN */
| (1 << 14);/* ETHMACEN */
/* enable MDIO */
GPIOA_CRL = (GPIOA_CRL & 0xFFFFF0FF) | 0x00000E00; /* PA2=AF OD 2 MHz */
/* enable MDC */
GPIOC_CRL = (GPIOC_CRL & 0xFFFFFF0F) | 0x000000A0; /* PC1=AF P-P 2 MHz */
...
}

static bool
smi_busy(void)
{
return !!REGBIT(ETH_MACMIIAR, 0);
}

static void
smi_write(int reg, int val)
{
ETH_MACMIIDR = val;
ETH_MACMIIAR = (reg << 6) | SMI_TMPL | 3;
while (smi_busy())
{
/* wait */
}
}

static void
smi_start_read(int reg)
{
ETH_MACMIIAR = (reg << 6) | SMI_TMPL | 1;
}

static int
smi_read_data(void)
{
return ETH_MACMIIDR;
}

static void
phy_init(void)
{
/* dummy read: the first read gets garbled for some reason */
smi_start_read(0);
while (smi_busy())
{
/* wait */
}
}