void MX_FMC_Init(void)
{
FMC_SDRAM_TimingTypeDef SdramTiming;

/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK2;//FMC_SDRAM_BANK2
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;//11
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;//1
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;//FMC_SDRAM_CLOCK_DISABLE
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;//FMC_SDRAM_RPIPE_DELAY_0
/* SdramTiming */
/* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */
/* TMRD: 2 Clock cycles */
SdramTiming.LoadToActiveDelay = 2;
/* TXSR: min=70ns (7x11.9ns) */
SdramTiming.ExitSelfRefreshDelay = 7;
/* TRAS: min=42ns (4x11.9ns) max=120k (ns) */
SdramTiming.SelfRefreshTime = 4;
/* TRC: min=70 (7x11.9ns) */
SdramTiming.RowCycleDelay = 7;
/* TWR: min=1+ 7ns (1+1x11.9ns) */
SdramTiming.WriteRecoveryTime = 2;
/* TRP: 20ns => 2x11.11ns */
SdramTiming.RPDelay = 2;
/* TRCD: 20ns => 2x11.11ns */
SdramTiming.RCDDelay = 2;

HAL_SDRAM_Init(&hsdram1, &SdramTiming);

}

uint8_t Array1[5] = {1,2,3,4,5};
uint8_t Array2[5] = {0,0,0,0,0};
#define BUFFER_SIZE ((uint32_t)0x0005)
#define WRITE_READ_ADDR ((uint32_t)0x0800)
#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)

/* Counter index */
volatile uint32_t uwIndex = 0x0000;


/* Write data to the SDRAM memory */
for (uwIndex = 0; uwIndex < BUFFER_SIZE; uwIndex++)
{
*(__IO uint8_t*) (SDRAM_BANK_ADDR + uwIndex) = Array1[uwIndex];
}

/* Read back data from the SDRAM memory */
for (uwIndex = 0; uwIndex < BUFFER_SIZE; uwIndex++)
{
Array2[uwIndex] = *(__IO uint8_t*) (SDRAM_BANK_ADDR + uwIndex);
}

static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
{
__IO uint32_t tmpmrd =0;
/* Step 3: Configure a clock configuration enable command */
Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
Command->AutoRefreshNumber = 1;
Command->ModeRegisterDefinition = 0;

/* Send the command */
HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);

/* Step 4: Insert 100 ms delay */
HAL_Delay(100);

/* Step 5: Configure a PALL (precharge all) command */
Command->CommandMode = FMC_SDRAM_CMD_PALL;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
Command->AutoRefreshNumber = 1;
Command->ModeRegisterDefinition = 0;

/* Send the command */
HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);

/* Step 6 : Configure a Auto-Refresh command */
Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
Command->AutoRefreshNumber = 4;
Command->ModeRegisterDefinition = 0;

/* Send the command */
HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);

/* Step 7: Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_3 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;

Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
Command->AutoRefreshNumber = 1;
Command->ModeRegisterDefinition = tmpmrd;

/* Send the command */
HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);

/* Step 8: Set the refresh rate counter */
/* (15.62 us x Freq) - 20 */
/* Set the device refresh counter */
HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
}

#define SDRAM_SIZE 0x00800000
uint8_t *p = (uint8_t *)SDRAM_BANK1_ADDR;

// Тест SDRAM
for ( i = 0; i < SDRAM_SIZE; i ++ )
{
*(p+i) = 0xFF - (uint8_t)i;
} // for

// Проверка
isOk = true;
for ( i = 0; i < SDRAM_SIZE; i ++ )
{
if ( *(p+i) != 0xFF - (uint8_t)i )
{
isOk = false;
break;
} // if
} // for

  // Send the command
  // SDCMR = 0x00000011 = xx 0001 0001
  //  MRD = 0
  //  NRFS = 0   - Clock Configuration Enable
  //  CTB1 = 1   - Command issued to SDRAM Bank 1
  //  CTB2 = 0   - Command not issued to SDRAM Bank 2
  //  MODE = 001 - Clock Configuration Enable
  FMC_SDRAMCmdConfig ( &FMC_SDRAMCommandStructure );