По-поводу тактов: делали 20 пустых - никакого эффекта, увеличивая на 10 тактов довели число пустых до 100 - тоже нет результата

Даиташит страница 8-7 - нужно 3192 пустых тактов.

When using the internal oscillator, you do not have to send additional clock cycles from an external source to the CLKUSR pin during the initialization stage.

Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.

nCONFIG подтягивается до +3.3В через порт GPIO на самом процессоре.

Yes, a pull-up or pull-down resistor helps keep the nCONFIG line in a known state when the external host (a Max® II CPLD or a microcontroller) is not driving the line (for example, during external host reprogramming or power-up where the I/O driving nCONFIG may be tri-stated). If a pull-up resistor is added to the nCONFIG line, the FPGA stays in user mode if the external host is being reprogrammed. If a pull-down resistor is added to the nCONFIG line, the FPGA goes into reset mode if the external host is being reprogrammed.

Whenever the nCONFIG line is released high, ensure the first DCLK and DATA are not driven unintentionally. Altera recommends to keep the nCONFIG line low if the external host or the FPGA is not ready for configuration.