void SDRAMInit( void )
{
volatile uint32_t i;
volatile unsigned long Dummy;

LPC_IOCON->P3_0 = 0x21;
LPC_IOCON->P3_1 = 0x21;
LPC_IOCON->P3_2 = 0x21;
LPC_IOCON->P3_3 = 0x21;
LPC_IOCON->P3_4 = 0x21;
LPC_IOCON->P3_5 = 0x21;
LPC_IOCON->P3_6 = 0x21;
LPC_IOCON->P3_7 = 0x21;

LPC_IOCON->P4_0 = 0x21;
LPC_IOCON->P4_1 = 0x21;
LPC_IOCON->P4_2 = 0x21;
LPC_IOCON->P4_3 = 0x21;
LPC_IOCON->P4_4 = 0x21;
LPC_IOCON->P4_5 = 0x21;
LPC_IOCON->P4_6 = 0x21;
LPC_IOCON->P4_7 = 0x21;
LPC_IOCON->P4_8 = 0x21;
LPC_IOCON->P4_9 = 0x21;
LPC_IOCON->P4_10 = 0x21;
LPC_IOCON->P4_11 = 0x21;
LPC_IOCON->P4_12 = 0x21;
LPC_IOCON->P4_13 = 0x21;
LPC_IOCON->P4_14 = 0x21;
LPC_IOCON->P4_15 = 0x21;
LPC_IOCON->P5_0 = 0x21;

LPC_IOCON->P4_24 = 0x21;
LPC_IOCON->P4_25 = 0x21;

LPC_IOCON->P4_31 = 0x00;
LPC_GPIO4->DIR |= (1<<31);
LPC_GPIO4->SET |= (1<<31);
LPC_IOCON->P4_30 = 0x21;
// EMC_Init();
// Init SDRAM controller
LPC_SC->PCONP |= 0x00000800;
/*Init SDRAM controller*/
/*Set data read delay*/
LPC_SC->EMCDLYCTL |= (8<<0);
LPC_SC->EMCDLYCTL |=(8<<8);

LPC_SC->EMCDLYCTL |= (8<<16);

LPC_EMC->Control = 0x01;
LPC_EMC->Config = 0x00;
LPC_EMC->StaticExtendedWait = 0x00;
LPC_EMC->StaticConfig0 = 0x00;
LPC_EMC->StaticWaitWen0 = 0x01;
LPC_EMC->StaticWaitOen0 = 0x01;
LPC_EMC->StaticWaitRd0 = 0x01;
LPC_EMC->StaticWaitWr0 = 0x01;
}

; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************

LR_IROM1 0x00000000 0x00080000  {   ; load region size_region
  ER_IROM1 0x00000000 0x00080000  { ; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }
  RW_IRAM1 0x10000000 0x00010000  { ; RW data
   .ANY (+RW +ZI)
  }
  
  RW_IRAM2 0x20000000 0x00007FFF  { ; RW data
.ANY (+RW +ZI)
  }
  
  RW_RAM1 0x80000000 UNINIT 0x02000000  { ; RW data
  ;rsramTesr.o (.data)
   sramTesr.o (.bss)
  
  }
}

unsigned char sramData[50];

u8 hello[] = "Hello!\r";
extern unsigned char sramData[50];

int main (void)
{
    SystemInit();

...
    /**< init sram */
    SRAMInit ();
    /** waiting after init */
       ...
    
    /** ложу данные  в sram*/
    for (u8 i = 0; i < 8; i++)
    {
        sramData[i] = hello[i];
    }

    /**  достаю данные из срама */
    for (u8 i=0; i<8; i++)
    {
        while (uart.readyToSend() == 0);
        uart.sendChar (sramData[i]); /** Отправляю в uart и смотрю что вышло. Данные не совпадают */
    }

    while(1)
    {
    }
}

    .bss                                     0x80000000   Section       50  sramtesr.o(.bss)

LR_IROM1 0x00000000 0x00080000  {   ; load region size_region
  ER_IROM1 0x00000000 0x00080000  { ; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }
  RW_IRAM1 0x10000000 0x00010000  { ; RW data
   .ANY (+RW +ZI)
  }
  
  RW_IRAM2 0x20000000 0x00007FFF  { ; RW data
    

  }
  
  RW_RAM1 0x80000000 UNINIT 0x0000FFFF  { ; RW data
{
    EMAC_LPC177x_8x.o (.bss)
  }
  
   RW_RAM2 0x81000000 UNINIT 0x0000FFFF  { ; RW data
    
  }
}

  RW_RAM1 0x80000000 UNINIT 0x0000FFFF  {; RW data
{
    EMAC_LPC177x_8x.o (.bss)
  }

  RW_RAM1 0x80000000 UNINIT 0x0000FFFF  {; RW data
{
    EMAC_LPC177x_8x.o
    EMAC_LPC177x_8x.o (.bss)
  }