void SystemInit(void)
{
CCM->CLPCR &= ~CCM_CLPCR_FXOSC_PWRDWN_MASK;

while(!(CCM_CSR_FXOSC_RDY_MASK & CCM->CSR));

CCM->CCSR |= CCM_CCSR_FAST_CLK_SEL_MASK;

// using PLL1 PFD3
//Enable CCM, SRC, and more
CCM->CCGR4 |= CCM_CCGR4_CG10(1); // WKPU ungate
CCM->CCGR4 |= CCM_CCGR4_CG11(1); // CCM ungate
CCM->CCGR4 |= CCM_CCGR4_CG12(1); // GPC ungate
CCM->CCGR4 |= CCM_CCGR4_CG14(1); // SRC ungate
CCM->CCGR3 |= CCM_CCGR3_CG0(1); // ANADIG ungate

//Enable IOMUX
CCM->CCGR2 |= CCM_CCGR2_CG8(1); // IOMUX Controller ungate
CCM->CCGR2 |= CCM_CCGR2_CG9(1); // Port A Controller ungate
CCM->CCGR2 |= CCM_CCGR2_CG10(1); // Port B Controller ungate
CCM->CCGR2 |= CCM_CCGR2_CG11(1); // Port C Controller ungate
CCM->CCGR2 |= CCM_CCGR2_CG12(1); // Port D Controller ungate
CCM->CCGR2 |= CCM_CCGR2_CG13(1); // Port E Controller ungate

/* enable PLLs in Anadig */
ANADIG->PLL1_CTRL=0x00002001;
while(!(ANADIG_PLL1_CTRL_LOCK_MASK & ANADIG->PLL1_CTRL));//wait until lock

ANADIG->PLL2_CTRL=0x00002001;
while(!(ANADIG_PLL2_CTRL_LOCK_MASK & ANADIG->PLL2_CTRL));//wait until lock
ANADIG->PLL4_CTRL=0x00002031; //PLL4
while(!(ANADIG_PLL4_CTRL_LOCK_MASK & ANADIG->PLL4_CTRL));//wait until lock
ANADIG->PLL5_CTRL=0x00002001; //PLL5
while(!(ANADIG_PLL5_CTRL_LOCK_MASK & ANADIG->PLL5_CTRL));//wait until lock
ANADIG->PLL6_CTRL=0x00002028; //PLL6
while(!(ANADIG_PLL6_CTRL_LOCK_MASK & ANADIG->PLL6_CTRL));//wait until lock

//Use 500MHz CA5, 400 MHz DDR(async), 166MHz CM4, and 83MHz bus (PFD1=500MHz)
//CCM->CCSR=0x0001FF24; //PLL1 uses PLL1_PFD3, enable all PLL1 and PLL2, select Fast Clock, and sys_clock_sel use PLL1
CCM->CCSR=0x0001FF24; //PLL1 uses PLL1_PFD3, enable all PLL1 and PLL2, select Fast Clock, and sys_clock_sel use PLL1
CCM->CACRR=0x00000810; //ARM_DIV=0 (div by 1), BUS_DIV=2 (div by 3), ipg_div value is 1 (div by 2)


}