Critical Warning: No exact pin location assignment(s) for 16 pins of 65 total pins

Потыкал проект, явного криминала в констрейнах не увидел (не значит, что его там нет). Частота памяти 150 МГц, но Fmax, которую выжал синтезатор - 122 МГц. Что насторожило: . Поскольку там речь идет о сигналах ddr_dq, это может быть причиной. Все большие частоты, которые встречаются в отчете относятся к Fmax, т.е. по большинству клоков огромный запас, это нормально.

отсюда растут проблемы типа "вчера все работало, сегодня изменил 1 бит и не работает"

надо подсоединить qsys к ногам, сделать анализ-синтез
потом запустить .tcl-скрипт который сообразит к каким ногам это всё подключено и допишет констрейны
после этого снова анализ-синтез-фиттер и тогда соберется нормально

If you are at the design exploration phase of your design cycle and do not have any PCB defined pin locations,
you must still manually define an initial set of pin constraints, which can become more specific during your
development process

To add the pin and I/O standards to the design example, perform the following steps:
1) On the Tools menu, click Tcl scripts.
2) Under Libraries, select <variation_name>_pin_assignments.tcl
3) Click Run

assignments -> device -> device and pin options -> pin options
ввести вручную сколько надо

Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Error (169015): Cannot place pin ddr_dq[8] to location B12
Error (169223): Can't place VREF pin C11 (VREFGROUP_B7_N0) for pin ddr_dq[8] of type bi-directional with SSTL-18 Class I I/O standard at location B12
Error (169224): Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin C11 (VREFGROUP_B7_N0) is used on device EP3C25F256I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info (169220): Location D11 (pad PAD_177): Pin ddr_ba[2] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location D12 (pad PAD_178): Pin ddr_ba[1] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location A13 (pad PAD_179): Pin ddr_ba[0] of type output uses SSTL-18 Class I I/O standard
Info (169225): Following 5 pins have the same output enable group 1: 3 pins require VREF pin and 5 pins could be output
Info (169220): Location B13 (pad PAD_180): Pin ddr_dq[15] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location E11 (pad PAD_183): Pin ddr_a[0] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location E10 (pad PAD_184): Pin ddr_a[2] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location A12 (pad PAD_186): Pin ddr_dq[14] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location A11 (pad PAD_188): Pin ddr_dq[9] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location A14 (pad PAD_181): Pin ddr_clk_n of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location B14 (pad PAD_182): Pin ddr_clk of type bi-directional uses SSTL-18 Class I I/O standard
Info (169222): Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info (169220): Location D11 (pad PAD_177): Pin ddr_ba[2] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location D12 (pad PAD_178): Pin ddr_ba[1] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location A13 (pad PAD_179): Pin ddr_ba[0] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location B13 (pad PAD_180): Pin ddr_dq[15] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location A14 (pad PAD_181): Pin ddr_clk_n of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location B14 (pad PAD_182): Pin ddr_clk of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location E11 (pad PAD_183): Pin ddr_a[0] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location E10 (pad PAD_184): Pin ddr_a[2] of type output uses SSTL-18 Class I I/O standard
Info (169221): Location (pad PAD_185): unused
Info (169220): Location A12 (pad PAD_186): Pin ddr_dq[14] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169221): Location B12 (pad PAD_187): unused (but has pin assignment of ddr_dq[8])
Info (169220): Location A11 (pad PAD_188): Pin ddr_dq[9] of type bi-directional uses SSTL-18 Class I I/O standard
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Error (171000): Can't fit design in device
Warning (169082): Design uses current of 400.0 mA for 15 consecutive horizontal output pads in an I/O bank -- Altera recommends a maximum current of 240.0 mA for any 14 consecutive output pads in an I/O bank
Warning (169082): Design uses current of 400.0 mA for 15 consecutive vertical output pads in an I/O bank -- Altera recommends a maximum current of 240.0 mA for any 12 consecutive output pads in an I/O bank
Warning (169180): Following 1 pins must use external clamping diodes.
Info (169178): Pin epcs_sdi uses I/O standard 2.5 V at H2
Warning (169064): Following 2 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
Info (169065): Pin ddr_clk has a permanently enabled output enable
Info (169065): Pin ddr_clk_n has a permanently enabled output enable
Error: Quartus II 32-bit Fitter was unsuccessful. 4 errors, 21 warnings
Error: Peak virtual memory: 326 megabytes
Error: Processing ended: Fri Oct 03 01:00:40 2014
Error: Elapsed time: 00:00:25
Error: Total CPU time (on all processors): 00:00:23

Там какая то замута есть, точно не помню.. Если вы проектируйте на х16 шину то все равно нужно смотреть столбец c x8/x9. Причем для первой группы 9й пин, который остался от предыдущей группы, в следующей использовать нельзя, а нужно пропустить его и перейти к следующей группе х8. Я перед тем как отправлять плату долго ковырялся в квартусе. то группы не совпадали, то еще чего. В общем гемор еще тот...