entity gertsel is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (9 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (9 downto 0));
end gertsel;

architecture arc_gertsel of gertsel is
constant coeff0:signed(10 downto 0):=to_signed(485,11);--integer range 0 to 1024;
signal n: integer range 0 to 35;
signal q0:signed(10 downto 0);--integer range 0 to 2048;
signal q1:signed(10 downto 0);--integer range 0 to 2048;
signal q2:signed(10 downto 0);--integer range 0 to 2048;
signal input:signed(9 downto 0);--integer range 0 to 1024;
signal output:signed(9 downto 0);--integer range 0 to 1024;
signal mul1: signed(26 downto 0);
signal mul2: signed(31 downto 0);
signal mul3: signed(31 downto 0);
signal mul4: signed(42 downto 0);
signal sum1: signed(42 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(reset='1') then
n<=0;
--q0<=0;
--q1<=0;
--q2<=0;
--coeff0<=879;
--output<=0;
q0<=(others=>'0');
q1<=(others=>'0');
q2<=(others=>'0');
mul1<=(others=>'0');
mul2<=(others=>'0');
mul3<=(others=>'0');
mul4<=(others=>'0');
sum1<=(others=>'0');
input<=(others=>'0');
output<=(others=>'0');
else
--********************************
if(en='1' and clk='1') then
input<=signed(x);--to_INTEGER(unsigned(x(9 downto 0)));
--input<=input-to_signed(511,10);
n<=n+1;
q2<=q1;
q1<=q0;
end if;
mul1<=(coeff0*q1)/1024;
q0<=mul1(9 downto 0)+input-511-q2;
if(n=36 ) then
n<=n+1;
mul2<=q1*q1/1024;
mul3<=q2*q2/1024;
mul4<=coeff0*q1*q1/1024;
sum1<=(mul2+mul3-mul4);

output(9 downto 0)<=sum1(9 downto 0);
y<=std_logic_vector(output);
end if;
if(n=37) then
q1<=(others=>'0');
q2<=(others=>'0');
end if;

--********************************
end if;
end if;
end process;

end arc_gertsel;