//////
//настраиваем порт
RCC->AHBENR |= RCC_AHBENR_GPIOCEN;
RCC->AHBENR |= RCC_AHBENR_GPIODEN;

GPIOC->OSPEEDR|= GPIO_OSPEEDER_OSPEEDR8|GPIO_OSPEEDER_OSPEEDR9|GPIO_OSPEEDER_OSPEEDR10|GPIO_OSPEE
DER_OSPEEDR11| GPIO_OSPEEDER_OSPEEDR11;
GPIOD->OSPEEDR|= GPIO_OSPEEDER_OSPEEDR2;

GPIOC->MODER &= ~GPIO_MODER_MODER8;
GPIOC->MODER |= GPIO_MODER_MODER8_1;
GPIOC->MODER &= ~GPIO_MODER_MODER9;
GPIOC->MODER |= GPIO_MODER_MODER9_1;
GPIOC->MODER &= ~GPIO_MODER_MODER10;
GPIOC->MODER |= GPIO_MODER_MODER10_1;
GPIOC->MODER &= ~GPIO_MODER_MODER11;
GPIOC->MODER |= GPIO_MODER_MODER11_1;
GPIOC->MODER &= ~GPIO_MODER_MODER12;
GPIOC->MODER |= GPIO_MODER_MODER12_1;

GPIOD->MODER &= ~GPIO_MODER_MODER2;
GPIOD->MODER |= GPIO_MODER_MODER2_1;

GPIOC->AFR[1]|=(12<<0);
GPIOC->AFR[1]|=(12<<4);
GPIOC->AFR[1]|=(12<<8);
GPIOC->AFR[1]|=(12<<12);
GPIOC->AFR[1]|=(12<<16);

GPIOD->AFR[0]|=(12<<8);

///////Настраиваем SDIO
RCC->APB2ENR|=RCC_APB2ENR_SDIOEN; // включаем тактирование

RCC->APB2RSTR|=RCC_APB2RSTR_SDIORST;
RCC->APB2RSTR&=~RCC_APB2RSTR_SDIORST; //сброс настроек

SDIO->CLKCR|=SDIO_CLKCR_HWFC_EN; //HW Flow Control is enabled
SDIO->CLKCR|=SDIO_CLKCR_WIDBUS_0; // 4-wide bus mode: SDIO_D[3:0] used
SDIO->CLKCR|=SDIO_CLKCR_PWRSAV; //SDIO_CK is only enabled when the bus is active
SDIO->CLKCR|=SDIO_CLKCR_CLKEN; //SDIO_CK is enabled

SDIO->CLKCR|=SDIO_CMD_CPSMEN; //Command path state machine (CPSM) Enable bit
SDIO->CLKCR|=SDIO_CMD_WAITPEND; //CPSM Waits for ends of data transfer

SDIO->DTIMER=400000; //Data timeout period

SDIO->DLEN=512; //Data length value

SDIO->DCTRL|=SDIO_DCTRL_SDIOEN;
SDIO->DCTRL|=SDIO_DCTRL_DTMODE; //SDIOEN=1 and DTMODE=1, the peripheral enables an SDIO multibyte transfer. //Непонятно, что это
SDIO->DCTRL|=SDIO_DCTRL_RWMOD; //Read Wait control using SDIO_CK ///Непонятно, что это
SDIO->DCTRL|=SDIO_DCTRL_DBLOCKSIZE_0 | SDIO_DCTRL_DBLOCKSIZE_3; // размер блока 512

///Пытаемся передать команту
char cmd=CMD0
while(1)
{
SDIO->CLKCR|=SDIO_CMD_WAITRESP_0; //Short response, expect CMDREND or CCRCFAIL flag
SDIO->CLKCR &=~ SDIO_CMD_WAITRESP_1;

SDIO->CLKCR|=SDIO_CMD_CPSMEN; //Command path state machine (CPSM) Enable bit

SDIO->CLKCR &=~ SDIO_CMD_CMDINDEX;
SDIO->CLKCR |=(cmd & SDIO_CMD_CMDINDEX);
SDIO->ARG=0;

}

The UART pins must be configured in the IOCON block before the UART clock can be enabled
in the in the SYSAHBCLKCTRL register (Table xx) for parts LPCxxxx....

The sequence of configuring the UART pins and the UART clock has no effect for
parts LPCxxxx/01 and ....

Описание периферийного модуля XXX:

2. Power: In the SYSAHBCLKCTRL register, set bit xx (Table xx).
3. Peripheral clock: Enable the UART peripheral clock by writing to the UARTCLKDIV
register (Table xx).

Remark: The XXX pins must be configured in the corresponding IOCON registers before the XXX clocks are enabled.