================================================================================
Timing constraint: COMP "ADCI<0>" OFFSET = IN -0.715 ns BEFORE COMP "CLK6I";

1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Offset is  -0.715ns.
--------------------------------------------------------------------------------
Slack:                  0.000ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               ADCI<0> (PAD)
  Destination:          DI_0 (FF)
  Destination Clock:    CLK20N rising at 0.000ns
  Requirement:          -0.715ns
  Data Path Delay:      5.464ns (Levels of Logic = 0)
  Clock Path Delay:     6.179ns (Levels of Logic = 4)
  Clock Uncertainty:    0.000ns

  Data Path: ADCI<0> to DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P47.ICLK1            Tiopickd              5.464   ADCI<0>
                                                       ADCI<0>
                                                       ADCI_0_IBUF
                                                       ADCI<0>.DELAY
                                                       DI_0
    -------------------------------------------------  ---------------------------
    Total                                      5.464ns (5.464ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Clock Path: CLK6I to DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P87.I                Tiopi                 1.530   CLK6I
                                                       CLK6I
                                                       IBUFG_inst
    DCM_X1Y1.CLKIN       net (fanout=1)        0.561   CLK6
    DCM_X1Y1.CLKFX       Tdcmino               0.014   DCM_inst
                                                       DCM_inst
    SLICE_X29Y47.G2      net (fanout=1)        1.250   CLK20
    SLICE_X29Y47.Y       Tilo                  0.441   _n0353
                                                       _n03531_INV_0
    BUFGMUX6.I0          net (fanout=1)        1.489   _n0353
    BUFGMUX6.O           Tgi0o                 0.001   BUFG_inst2
                                                       BUFG_inst2
    P47.ICLK1            net (fanout=605)      0.893   CLK20N
    -------------------------------------------------  ---------------------------
    Total                                      6.179ns (1.986ns logic, 4.193ns route)
                                                       (32.1% logic, 67.9% route)

--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK6I
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
ADCI<0>     |   -0.715(R)|    4.209(R)|CLK20N            |   0.000|
------------+------------+------------+------------------+--------+