...
ADC1_DIFF_BUF : IBUFDS
generic map( DIFF_TERM => FALSE,
IOSTANDARD => "LVDS_25")
port map( I => ADC1_DCO_p,
IB => ADC1_DCO_n,
O => ADC1_DCO);
ADC1_DCO_BUFG: BUFG
port map(
I => ADC1_DCO,
O => ADC1_CLKIN);
ADC1_PLL:PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => 2.5,
CLKIN2_PERIOD => 2.5,
CLKOUT0_DIVIDE => 1,
CLKOUT1_DIVIDE => 4,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 1,
-- CLKFBOUT_MULT => 2,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.1,
SIM_DEVICE => "SPARTAN6"
)
port map
(
CLKFBIN => ADC1_CLKFB,
CLKINSEL => '1',
CLKIN1 => ADC1_CLKIN,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => reset,
CLKFBDCM => open,
CLKFBOUT => ADC1_CLKFB,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => ADC1_CLK,
CLKOUT1 => ADC1_DCLK,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => ADC1_PLL_LOCKED
);

ADC1_BUFFPLL:BUFPLL
generic map( DIVIDE => 4,
ENABLE_SYNC => TRUE)
port map ( PLLIN => ADC1_CLK,
-- GCLK => ADC1_DIVCLK,
GCLK => DIVCLK,
LOCKED => ADC1_PLL_LOCKED,
IOCLK => ADC1_SerDes_CLK,
SERDESSTROBE => ADC1_SerDes_Strobe,
LOCK => adc1_bufpll_locked
);
ADC1_DCLK_BUF : BUFG
port map( I => ADC1_DCLK,
O => ADC1_DIVCLK);

--ADC2_DIFF_BUF : IBUFDS
-- generic map( DIFF_TERM => TRUE,
-- IOSTANDARD => "LVDS_25")
-- port map( I => ADC2_DCO_p,
-- IB => ADC2_DCO_n,
-- O => ADC2_DCO);
--test_out<=ADC2_DCO;
--ADC2_DCO_BUFG: BUFG
-- port map(
-- I => ADC2_DCO,
---- I => ADC2_DCO_BUF,
-- O => ADC2_CLKIN);
ADC2_CLKIN<='0';
ADC2_PLL:PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => 2.5,
CLKIN2_PERIOD => 2.5,
CLKOUT0_DIVIDE => 1,
CLKOUT1_DIVIDE => 4,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 1,
-- CLKFBOUT_MULT => 2,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.1,
SIM_DEVICE => "SPARTAN6"
)
port map
(
CLKFBIN => ADC2_CLKFB,
CLKINSEL => '1',
CLKIN1 => ADC2_CLKIN,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => reset,
CLKFBDCM => open,
CLKFBOUT => ADC2_CLKFB,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => ADC2_CLK,
CLKOUT1 => ADC2_DCLK,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => ADC2_PLL_LOCKED
);

ADC2_BUFFPLL:BUFPLL
generic map( DIVIDE => 4,
ENABLE_SYNC => TRUE)
port map ( PLLIN => ADC2_CLK,
-- GCLK => ADC2_DIVCLK,
GCLK => DIVCLK,
LOCKED => ADC2_PLL_LOCKED,
IOCLK => ADC2_SerDes_CLK,
SERDESSTROBE => ADC2_SerDes_Strobe,
LOCK => adc2_bufpll_locked
);

ADC2_DCLK_BUF : BUFG
port map( I => ADC2_DCLK,
O => ADC2_DIVCLK);
...