module fpga (

    //loaner IOs
    inout           hps_gpio_LOANIO48,

    // FPGA
    // clock and reset
    input           fpga_clk_25,
    input           fpga_reset_n,

    // pio
    output          fpga_pio    
    );

    // wire instances of the 3 loan IO buses from Qsys instance
    wire    [66:0]  loan_io_in;
    wire    [66:0]  loan_io_out;
    wire    [66:0]  loan_io_oe;



    // loan_io    
    // cpu_led
    assign loan_io_out[48] = led_export;
    assign loan_io_in[48] = 1'b0;
    assign loan_io_oe[48] = 1'b1;
    
    assign fpga_pio = led_export;

    altpll_dev u0 (
        .rst            (~fpga_reset_n),
        .refclk         (fpga_clk_25),
        .outclk_0       (pll_clk_50),
        .locked         (pll_locked)
    );

    soc_system u1 (
        // HPS
        .hps_io_hps_io_gpio_inst_LOANIO48   (hps_gpio_LOANIO48),

        .hps_loan_io_in                     (loan_io_in),
        .hps_loan_io_out                    (loan_io_out),
        .hps_loan_io_oe                     (loan_io_oe),

        // FPGA
        .clk_50_clk                         (pll_clk_50),
        .reset_50_reset_n                   (pll_locked),
        
        .led_export                         (led_export),
    );
    
endmodule //fpga