(
        clock              : in std_logic;
        reset              : in std_logic;
        
        data_input         : in std_logic_vector(31 downto 0);
        data_flag          : in std_logic;

        done                  : out std_logic;
        data_ready         : out std_logic
)

signal reset_corebuf              : std_logic_vector(NCORES - 1 downto 0);
signal data_input_corebuf         : std_logic_vector((NCORES * 32) - 1 downto 0);
signal data_flag_corebuf          : std_logic_vector(NCORES - 1 downto 0);
signal done_corebuf                 : std_logic_vector(NCORES - 1 downto 0);
signal data_ready_corebuf         : std_logic_vector(NCORES - 1 downto 0);

    process (clk)
    begin
        if (rising_edge(clk)) then
            for i in 0 to NCORES - 1 loop
                reset_corebuf(i) <= reset;
                data_input_corebuf((i + 1) * 32 - 1 downto i * 32) <= core_data;
                data_flag_corebuf(i) <= data_core_flag(i);
                
                core_done(i) <= done_corebuf(i);
                data_core_ready(i) <= data_ready_corebuf(i);
            end loop;
        end if;
    end process;

MTMainCores:
    for i in 0 to NCORES - 1 generate
    begin
        CoreEntry: CRMain
        GENERIC MAP
        (
            CORE_N => i
        )
        PORT MAP
        (
            clock => clk,
            reset => reset,
            data_input => core_data,
            data_flag => data_core_flag(i),
            done => core_done(i),
            data_ready => data_mt_ready(i)
        );
    end generate MainCores;

attribute keep : string;  
attribute keep of reset_corebuf: signal is "true";  
attribute keep of data_input_corebuf: signal is "true";  
attribute keep of data_flag_corebuf: signal is "true";  
attribute keep of done_corebuf: signal is "true";  
attribute keep of data_ready_corebuf: signal is "true";

Paths for end point Mmux__n4665412_FRB (SLICE_X98Y138.D3), 312 paths
--------------------------------------------------------------------------------
Slack (setup path):     -2.621ns (requirement - (data path - clock path skew + uncertainty))
   Source:               MTMainCores[3].CoreEntry/data_ready_BRB2 (FF)
   Destination:          Mmux__n4665412_FRB (FF)
   Requirement:          5.000ns
   Data Path Delay:      7.486ns (Levels of Logic = 5)
   Clock Path Skew:      -0.100ns (1.521 - 1.621)
   Source Clock:         clk_BUFGP rising at 0.000ns
   Destination Clock:    clk_BUFGP rising at 5.000ns
   Clock Uncertainty:    0.035ns
  
   Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
     Total System Jitter (TSJ):  0.070ns
     Total Input Jitter (TIJ):   0.000ns
     Discrete Jitter (DJ):       0.000ns
     Phase Error (PE):           0.000ns
  
   Maximum Data Path at Slow Process Corner: MTMainCores[3].CoreEntry/data_ready_BRB2 to Mmux__n4665412_FRB
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     SLICE_X70Y134.DQ     Tcko                  0.337   MTMainCores[3].CoreEntry/data_ready_BRB2
                                                        MTMainCores[3].CoreEntry/data_ready_BRB2
     SLICE_X70Y132.C1     net (fanout=1)        0.710   MTMainCores[3].CoreEntry/data_ready_BRB2
     SLICE_X70Y132.C      Tilo                  0.068   data_mt_ready<3>
                                                        MTMainCores[3].CoreEntry/data_ready_rstpot
     SLICE_X97Y70.B3      net (fanout=5)        2.967   data_ready_corebuf<3>
     SLICE_X97Y70.B       Tilo                  0.068   data_mt_ready<7>
                                                        Mmux__n466542
     SLICE_X98Y112.D6     net (fanout=1)        1.627   N19372
     SLICE_X98Y112.D      Tilo                  0.068   MTMainCores[21].CoreEntry/SM_STATE_FSM_FFd4_BRB1
                                                        Mmux__n466544
     SLICE_X98Y138.C5     net (fanout=1)        1.158   N19376
     SLICE_X98Y138.C      Tilo                  0.068   Mmux__n4665412_FRB
                                                        N19384
     SLICE_X98Y138.D3     net (fanout=1)        0.345   N19384
     SLICE_X98Y138.CLK    Tas                   0.070   Mmux__n4665412_FRB
                                                        Mmux__n4665412
                                                        Mmux__n4665412_FRB
     -------------------------------------------------  ---------------------------
     Total                                      7.486ns (0.679ns logic, 6.807ns route)
                                                        (9.1% logic, 90.9% route)