void ClockInit(void)
{
EFC0->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE; // FWS = 2 = 3 такта ожидания при доступе к FLASH при 48 МГц
PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD; // разрешаем запись в PMC

PMC->PMC_SCDR = 0x78; // выключаем тактирование всей периферии
PMC->PMC_PCDR0 = 0xFFFFFF00;
PMC->PMC_PCDR1 = 0x00000007;

//Switch to slow RC
PMC -> PMC_MCKR = PMC_MCKR_CSS_SLOW_CLK;

//Enabling the Main Oscillator:
//SCK = 1/32768 = 30.51 uSecond
//Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
CKGR_MOR_MOSCXTST(255);
/* Wait the Xtal to stabilize */
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));

PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0); // выключаем PLL


//Setting PLL and divider:
//- div by 5 Fin = 3,6864 =(18,432 / 5)
//- Mul 25+1: Fout = 95,8464 =(3,6864 *26)
//for 96 MHz the erroe is 0.16%
//Field out NOT USED = 0
//PLLCOUNT pll startup time estimate at : 0.844 ms
//PLLCOUNT 28 = 0.000844 /(1/32768)
//pPMC->PMC_PLLR = ((5 | (AT91C_CKGR_PLLCOUNT & (28<<8)) | (AT91C_CKGR_MUL & (25<<16)));
PMC->CKGR_PLLAR = (CKGR_PLLAR_ONE | CKGR_PLLAR_PLLACOUNT(28) | CKGR_PLLAR_MULA(25) | CKGR_PLLAR_DIVA(5));

// Wait the startup time
while(!(PMC->PMC_SR & PMC_SR_LOCKA));
while(!(PMC->PMC_SR & PMC_SR_MCKRDY));

//Selection of Master Clock and Processor Clock
//select the PLL clock divided by 2
//pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_4;
PMC->PMC_MCKR = PMC_MCKR_CSS_PLLA_CLK | PMC_MCKR_PLLADIV2;
while(!(PMC->PMC_SR & PMC_SR_MCKRDY));

PMC->PMC_PCER0 = 0xFFFFFF00; // включаем тактирование всей периферии
PMC->PMC_PCER1 = PMC_PCER1_PID34; // тактирование USB
PMC->PMC_SCER = PMC_SCER_UDP;
}