-- Quartus II VHDL Template
-- Single port RAM with single read/write address

library ieee;
use ieee.std_logic_1164.all;

entity single_port_ram is

    port
    (
        clk        : in std_logic;
        addr    : in natural range 0 to 31;
        data    : in std_logic_vector(7 downto 0);
        we        : in std_logic := '1';
        q        : out std_logic_vector(7 downto 0)
    );

end entity;

architecture rtl of single_port_ram is

    -- Build a 2-D array type for the RAM
    subtype word_t is std_logic_vector(7 downto 0);
    type memory_t is array(256 downto 0) of word_t;

    -- Declare the RAM signal.    
    signal ram : memory_t;

    -- Register to hold the address
    signal addr_reg : natural range 0 to 256;

begin

    process(clk, we)
    begin
    if(rising_edge(clk)) then
        if(we = '1') then
            ram(addr) <= data;
        end if;
        addr_reg <= addr;
    end if;
    end process;

    q <= ram(addr_reg);
end rtl;

process(clk, we)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(addr) <= data;
end if;
q <= ram(addr);
end if;
end process;

process(clk, we)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(addr) <= data;
q <= data;
else
q <= ram(addr);
end if;
end if;
end process;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;

entity memA is
generic
    (
        DATA_WIDTH : natural := 4;
        ADDR_WIDTH : natural := 13
    );

    port
    (
        clk_a    : in std_logic;
        clk_b    : in std_logic;
        addr_a    : in std_logic_vector((ADDR_WIDTH-1) downto 0);
        addr_b    : in std_logic_vector((ADDR_WIDTH-1) downto 0);
        data_a    : in std_logic_vector((DATA_WIDTH-1) downto 0);
        data_b    : in std_logic_vector((DATA_WIDTH-1) downto 0);
        we_a    : in std_logic := '1';
        we_b    : in std_logic := '1';
        q_a        : out std_logic_vector((DATA_WIDTH -1) downto 0);
        q_b        : out std_logic_vector((DATA_WIDTH -1) downto 0)
    );          
          
end memA;

architecture Behavioral of memA is

    -- Build a 2-D array type for the RAM
    subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
    type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
    
    shared variable ram : memory_t:= (others => (others => '0'));
--     signal ram : memory_t :=
--(
-- to initialize memory
--    );
     signal mem_data : std_logic_vector (14 downto 0);
    
attribute ramstyle : string;
attribute ramstyle of ram : variable is "M9K, no_rw_check";
    
    
begin

    -- Port A
    process(clk_a)
    begin
    if(rising_edge(clk_a)) then
        if(we_a = '1') then
            ram(conv_integer(addr_a)) := data_a;
        end if;
        q_a <= ram(conv_integer(addr_a));
    end if;
    end process;

    -- Port B
    process(clk_b)
    begin
    if(rising_edge(clk_b)) then
        if(we_b = '1') then
            ram(conv_integer(addr_b)) := data_b;
        end if;
        q_b <= ram(conv_integer(addr_b));
    end if;
    end process;        

end Behavioral;

library ieee;
use ieee.std_logic_1164.all;

entity analyzer_mem is
generic (
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
port (
clk : in std_logic;
wr_addr : in natural range 0 to 2**ADDR_WIDTH - 1;
rd_addr : in natural range 0 to 2**ADDR_WIDTH - 1;
data_i : in std_logic_vector((DATA_WIDTH-1) downto 0);
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH -1) downto 0)
);

end analyzer_mem;

architecture rtl of analyzer_mem is

-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;

-- Declare the RAM
shared variable ram : memory_t;

begin

process(clk, rd_addr)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(wr_addr) := data_i;
end if;
end if;
q <= ram(rd_addr);
end process;

end rtl;