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-- Company:
-- Engineer:
--
-- Create Date:    13:52:23 06/08/2015
-- Design Name:
-- Module Name:    Clock_Detector - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Clock_Detector is
    Generic (
      Alarm_time      : integer range 2 to 250000 := 4
    );
    Port ( ClkX : in  STD_LOGIC;
           Clk : in  STD_LOGIC;
           Detect : out  STD_LOGIC);
end Clock_Detector;

architecture Behavioral of Clock_Detector is

  function getlog2 (int : in integer) return integer is
    variable log2 : natural := 0;
  begin
    if (int = 0) then
      log2 := 0;
    elsif (int <= 2) then
      log2 := 1;
    else
      log2 := getlog2((int/2) + (int rem 2)) + 1;
    end if;
    return log2;
  end function getlog2;

constant Count_MSB         : natural := getlog2(Alarm_Time);
  
signal Not_Use :std_logic;
signal ClkX_Shift : std_logic;
signal ClkX_Shift1 : std_logic;
signal ClkX_Rise_Sync: std_logic;
signal Count :std_logic_vector(Count_MSB downto 0);
alias Overflow: std_logic is Count(Count_MSB);

begin

process (Clk)
begin  
   if (Clk'event and Clk = '1') then
     Not_Use <= ClkX;
     ClkX_Shift <= Not_Use;
     ClkX_Shift1 <= ClkX_Shift;
   end if;
end process;

ClkX_Rise_Sync <= not ClkX_Shift1 and ClkX_Shift;

process (Clk, ClkX_Rise_Sync)
begin
   if ClkX_Rise_Sync='1' then
      Count <= conv_std_logic_vector((2**Count_MSB-Alarm_Time),Count_MSB+1);
   elsif Clk='1' and Clk'event then
      if (not Overflow)='1' then
         Count <= Count + 1;
      end if;
   end if;
end process;

Detect <= not Overflow;

end Behavioral;

module clk_los_ctrl
#(
parameter int pREFFREQ_HZ = 48_000_000 ,
parameter int pFREQ_HZ = 48_000_000 ,
parameter int pPPM = 100
)
(
iclk ,
ireset ,
irefclk ,
olos
);

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------

input logic iclk ;
input logic ireset ;
input logic irefclk ;
output logic olos ;

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------

localparam int cCLK_CNT_W = clogb2(pFREQ_HZ);
localparam bit [63 : 0] cPPMFREQ = (pREFFREQ_HZ * pPPM)/1_000_000 ;
localparam int cREFCLK_CNT_W = clogb2(pREFFREQ_HZ + cPPMFREQ);

logic [cREFCLK_CNT_W-1 : 0] refclk_cnt;
logic refclk_window_start;
logic refclk_window_end;
logic refclk_window;
logic refclk_done;

logic clr;
logic clr_at_clk;

logic ppm_ok;

logic [cCLK_CNT_W-1 : 0] clk_cnt;
logic clk_cnt_done;
logic clk_cnt_done_at_ref_clk;
//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------
// synthesis translate_off
initial begin : ini
refclk_cnt = '0;
refclk_window_start = '0;
refclk_window_end = '0;
refclk_window = '0;
refclk_done = '0;

clr = '0;
ppm_ok = '0;

clk_cnt = '0;
clk_cnt_done = '0;
end
// synthesis translate_on
//------------------------------------------------------------------------------------------------------
// count reference frequency
//------------------------------------------------------------------------------------------------------

always_ff @(posedge irefclk) begin
if (clr)
refclk_cnt <= '0;
else
refclk_cnt <= refclk_cnt + 1'b1;
//
// window
refclk_window_start <= (refclk_cnt == (pREFFREQ_HZ - cPPMFREQ - 2));
refclk_window_end <= (refclk_cnt == (pREFFREQ_HZ + cPPMFREQ - 2));

if (refclk_window_start)
refclk_window <= 1'b1;
else if (refclk_window_end)
refclk_window <= 1'b0;
//
// decision
{clr, refclk_done} <= {refclk_done, refclk_window_end};

if (refclk_window & clk_cnt_done_at_ref_clk)
ppm_ok <= 1'b1;
else if (refclk_done) begin
ppm_ok <= 1'b0;
olos <= ~ppm_ok;
end
end

//------------------------------------------------------------------------------------------------------
// synchronizers
//------------------------------------------------------------------------------------------------------

pulse_synchronizer
#(
.pLENGTH ( 3 )
)
clk_cnt_done_synchronizer // iclk -> irefclk
(
.clkin ( iclk ) , .resetin ( 1'b0 ) , .sin ( clk_cnt_done ) ,
.clkout ( irefclk ) , .resetout ( ) , .sout ( clk_cnt_done_at_ref_clk )
);

pulse_synchronizer
#(
.pLENGTH ( 3 )
)
clr_cnt__synchronizer // irefclk -> iclk
(
.clkin ( irefclk ) , .resetin ( 1'b0 ) , .sin ( clr ) ,
.clkout ( iclk ) , .resetout ( ) , .sout ( clr_at_clk )
);

//------------------------------------------------------------------------------------------------------
// count frequency
//------------------------------------------------------------------------------------------------------

always_ff @(posedge iclk) begin
if (clr_at_clk) begin
clk_cnt <= '0;
clk_cnt_done <= 1'b0;
end
else begin
clk_cnt <= clk_cnt + 1'b1;
clk_cnt_done <= (clk_cnt == (pFREQ_HZ-1));
end
end


endmodule

process (Clk, ClkX_Rise_Sync)
begin
  if Clk='1' and Clk'event then
    if ClkX_Rise_Sync='1' then
      Count <= conv_std_logic_vector((2**Count_MSB-Alarm_Time),Count_MSB+1);
    elsif (not Overflow)='1' then
         Count <= Count + 1;
    end if;
  end if;
end process;

module FreqDetector #(parameter BITS=3)
(
input clk,
input freq_pulse,
output freq_detected
)

reg [BITS-1:0] dly_line;

always @(posedge clk)
dly_line <= (dly_line<<1) |  freq_pulse;

assign freq_detect = | dly_line;

endmodule