// separating I and Q components of the input signal
wire signed [DIN_BW-1 : 0] din_i, din_q;
assign din_i = din_axis_tdata[DIN_BW-1 : 0];
assign din_q = din_axis_tdata[AXIS_DATA_BW-1 : DIN_BW];

// pipeline register inside of adder block
(* use_dsp48 = "yes" *) reg signed [SUM_DATA_BW-1 : 0] din_i_pp_int, din_q_pp_int;
reg din_valid_pp; // register to time align with internal data pipeline above
// result of adder
(* use_dsp48 = "yes" *) reg signed [SUM_DATA_BW-1 : 0] sum_i_acc, sum_q_acc;
always @(posedge clk) begin
din_i_pp_int <= {{DBF_BW_INCR{din_i[DIN_BW-1]}}, din_i};
din_q_pp_int <= {{DBF_BW_INCR{din_q[DIN_BW-1]}}, din_q};
din_valid_pp <= din_axis_tvalid;
end

// accumulator with reset
always @(posedge clk) begin
if(!din_valid_pp) begin
sum_i_acc <= 0;
sum_q_acc <= 0;
end else begin
sum_i_acc <= sum_i_acc + din_i_pp_int;
sum_q_acc <= sum_q_acc + din_q_pp_int;
end
end

attribute use_dsp48 : string;
attribute use_dsp48 of add_example : entity is "yes";