library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led is
    Port ( clk_100 : in  STD_LOGIC;
           led_1 : out  STD_LOGIC);
end led;

architecture Behavioral of led is

    constant prescaler: STD_LOGIC_VECTOR(23 downto 0) := "101111101011110000100000"; -- 12,500,000 in binary
    signal prescaler_counter: STD_LOGIC_VECTOR(23 downto 0) := (others => '0');
    signal newClock : std_logic := '0';

begin

led_1 <= newClock;

countClock: process(clk_100, newClock)
begin
    if rising_edge(clk_100) then
        prescaler_counter <= prescaler_counter + 1;
        if(prescaler_counter > prescaler) then
            -- Iterate
            newClock <= not newClock;

            prescaler_counter <= (others => '0');
        end if;
    end if;
end process;


end Behavioral;