-- Module Name: my_fifo - Behavioral
-- Description: A 32 x 9 FIFO using inferred storage

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity my_fifo is
Port ( clk : in STD_LOGIC;
wr : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(8 downto 0);
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(8 downto 0));
end my_fifo;

architecture Behavioral of my_fifo is
signal i_full : std_logic;
signal i_empty : std_logic;

type mem_array is array(31 downto 0) of std_logic_vector(8 downto 0);
signal memory : mem_array;
signal wr_ptr : unsigned(4 downto 0) := (others => '0');
signal rd_ptr : unsigned(4 downto 0) := (others => '0');

begin
full <= i_full;
empty <= i_empty;

flag_proc: process(wr_ptr, rd_ptr)
begin
if wr_ptr = rd_ptr then
i_empty <= '1';
else
i_empty <= '0';
end if;

if wr_ptr+1 = rd_ptr then
i_full <= '1';
else
i_full <= '0';
end if;
end process;

clk_proc: process(clk)
begin
if rising_edge(clk) then
if rd = '1' then
if wr = '1' then
if i_empty = '0' then
dout <= memory(to_integer(rd_ptr));
rd_ptr <= rd_ptr + 1;
end if;

memory(to_integer(wr_ptr)) <= din;
wr_ptr <= wr_ptr + 1;

elsif i_empty = '0' then
dout <= memory(to_integer(rd_ptr));
rd_ptr <= rd_ptr + 1;
end if;
elsif wr = '1' then
if i_full = '0' then
memory(to_integer(wr_ptr)) <= din;
wr_ptr <= wr_ptr + 1;
end if;
end if;
end if;
end process;
end Behavioral;