if (C'event and C='1')then  
          if (CE='1') then

if rd'event and rd='1' then
Ard <= Ard + 2; --адреса преребираем через два т.к. шина PCI 32 разряда
end if;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity memA0 is
generic
(
DATA_WIDTH : natural := 4;
ADDR_WIDTH : natural := 13
);

port
(
clk_a : in std_logic;
clk_b : in std_logic;
addr_a : in std_logic_vector((ADDR_WIDTH-1) downto 0);
addr_b : in std_logic_vector((ADDR_WIDTH-1) downto 0);
data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
we_a : in std_logic := '1';
we_b : in std_logic := '1';
q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
);

end memA0;

architecture Behavioral of memA0 is

-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;

shared variable ram : memory_t:= (others => (others => '0'));
-- signal ram : memory_t :=
--(
-- to initialize memory
-- );
signal mem_data : std_logic_vector (14 downto 0);


begin

-- Port A
process(clk_a)
begin
if(rising_edge(clk_a)) then
if(we_a = '1') then
ram(conv_integer(addr_a)) := data_a;
end if;
q_a <= ram(conv_integer(addr_a));
end if;
end process;

-- Port B
process(clk_b)
begin
if(rising_edge(clk_b)) then
if(we_b = '1') then
ram(conv_integer(addr_b)) := data_b;
end if;
q_b <= ram(conv_integer(addr_b));
end if;
end process;

end Behavioral;