#**************************************************************
# Set Input Delay
#**************************************************************
create_clock -period $tDCO -name {virt_clk_in}
set_clock_groups -asynchronous -group {virt_clk_in} -group {ClkAdc}
# clock source to source clock pin delay
set clkAs_delay_max 0.0
#[expr 30.0*0.010]
set clkAs_delay_min 0.0
#[expr 30.0*0.005]
# clock source to destination clock pin delay
# 30mm 0.010 ns/mm
set clkAd_delay_max [expr 30.0*0.010]
set clkAd_delay_min [expr 30.0*0.005]
# source to destination data pins delay
set bdA_delay_max [expr 30.0*0.010]
set bdA_delay_min [expr 30.0*0.005]
#ADC parameters AD9634
set tPD_min 4.1
set tPD_max 5.2
set tDCO_min 4.7
set tDCO_max 5.8
set tCLK     9.3
set Tco_max [expr $tCLK/2 - $tDCO_min + $tPD_max]
set Tco_min [expr $tCLK/2 - $tDCO_max + $tPD_min]
#set Tco_max 6.5
#set Tco_min 2.5
set usedTsu [expr $clkAs_delay_max + $Tco_max + $bdA_delay_max - $clkAd_delay_min]
set usedTh [expr $clkAs_delay_min + $Tco_min + $bdA_delay_min - $clkAd_delay_max]
set_input_delay -clock {virt_clk_in} -max $usedTsu [get_ports {InAdc[*]}]
set_input_delay -clock {virt_clk_in} -min $usedTh [get_ports {InAdc[*]}]
post_message "**********************************************************"
post_message "***Tco_max = $Tco_max ns"
post_message "***Tco_min = $Tco_min ns"
post_message "***usedTsu = $usedTsu ns"
post_message "***usedTh = $usedTh ns"
post_message "**********************************************************"

module slacks #(parameter pDAT_W = 14) (input Clk, input [pDAT_W-1 : 0] Din, output logic [pDAT_W-1 : 0] dout_re, dout_im);

  logic [pDAT_W-1 : 0] ddio__dataout_h;
  logic [pDAT_W-1 : 0] ddio__dataout_l;
  logic [pDAT_W-1 : 0] dat_re [2];
  logic [pDAT_W-1 : 0] dat_im [2];

  altddio_in
  #(
    .intended_device_family ( "Cyclone V"  ) ,
    .invert_input_clocks    ( "OFF"         ) ,
    .lpm_hint               ( "UNUSED"     ) ,
    .lpm_type               ( "altddio_in" ) ,
    .power_up_high          ( "OFF"        ) ,
    .width                  ( pDAT_W       )
  )
  ddio
  (
    .datain     ( Din             ),
    .inclock    ( Clk             ),
    .dataout_h  ( ddio__dataout_h ),
    .dataout_l  ( ddio__dataout_l ),
    .aclr (1'b0),
    .aset (1'b0),
    .inclocken (1'b1),
    .sclr (1'b0),
    .sset (1'b0)
  );

  always_ff @(posedge Clk) begin
    {dat_re[1], dat_re[0]} <= {dat_re[0], ddio__dataout_h};
    {dat_im[1], dat_im[0]} <= {dat_im[0], ddio__dataout_l};
    //
    dout_re <= dat_re[1];
    dout_im <= dat_im[1];
  end

endmodule

set_time_format -unit ns -decimal_places 3

set CLK_PERIOD 4.0

create_clock -name {Clk} -period $CLK_PERIOD [get_ports {Clk}]

set tskew_min 0.4
set tskew_max 1.0

# setup
set_input_delay -clock {Clk}                     -rise -max  1.0   [get_ports {Din[*]}] -add_delay
set_input_delay -clock {Clk} -clock_fall     -fall -max  1.0     [get_ports {Din[*]}] -add_delay

# hold
set_input_delay -clock {Clk}                     -rise -min -0.4     [get_ports {Din[*]}] -add_delay
set_input_delay -clock {Clk} -clock_fall     -fall -min -0.4     [get_ports {Din[*]}] -add_delay

# remove incorrect from-to paths
set_false_path -rise_from [get_clocks {Clk}] -through [get_pins -compatibility_mode ddio*\|datain] -fall_to [get_clocks {Clk}]
set_false_path -fall_from [get_clocks {Clk}] -through [get_pins -compatibility_mode ddio*\|datain] -rise_to [get_clocks {Clk}]