type std_logic_array_64xNN is array (511 downto 0) of std_logic_vector(63 downto 0);

-- Инициализирую массив 512х64 функцией read_ini_file.
constant const_init : std_logic_array_64xNN:=read_ini_file(stage_num);

attribute RAM_STYLE : string;
attribute RAM_STYLE of d_out : signal is "block";

begin    
    -- адрес = выход обычного счетчика
    addr <= cnt(stage_num-2 downto 0);    
    -- здесь я пытаюсь сделать ROM 512х64 на BRAM:
    d_out <= const_init(conv_integer(addr)) when rising_edge(clk);

library ieee;
use ieee.std_logic_1164.all;

entity true_dual_port_ram_single_clock is

    generic
    (
        DATA_WIDTH : natural := 8;
        ADDR_WIDTH : natural := 6
    );

    port
    (
        clk        : in std_logic;
        addr_a    : in natural range 0 to 2**ADDR_WIDTH - 1;
        addr_b    : in natural range 0 to 2**ADDR_WIDTH - 1;
        data_a    : in std_logic_vector((DATA_WIDTH-1) downto 0);
        data_b    : in std_logic_vector((DATA_WIDTH-1) downto 0);
        we_a    : in std_logic := '1';
        we_b    : in std_logic := '1';
        q_a        : out std_logic_vector((DATA_WIDTH -1) downto 0);
        q_b        : out std_logic_vector((DATA_WIDTH -1) downto 0)
    );

end true_dual_port_ram_single_clock;

architecture rtl of true_dual_port_ram_single_clock is

    -- Build a 2-D array type for the RAM
    subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
    type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;

    -- Declare the RAM
    shared variable ram : memory_t;

begin


    -- Port A
    process(clk)
    begin
    if(rising_edge(clk)) then
        if(we_a = '1') then
            ram(addr_a) := data_a;
        end if;
        q_a <= ram(addr_a);
    end if;
    end process;

    -- Port B
    process(clk)
    begin
    if(rising_edge(clk)) then
        if(we_b = '1') then
            ram(addr_b) := data_b;
        end if;
          q_b <= ram(addr_b);
    end if;
    end process;

end rtl;

process (clk)
    variable ram : ram_t;
begin
    if clk'event and clk = '1' then
        if wr_en = '1' then
            ram(conv_integer(addr)) := data_in;
        end if;
        data_out <= ram(conv_integer(addr));
    end if;
end process;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity single_port_rom is

    generic
    (
        DATA_WIDTH : natural := 8;
        ADDR_WIDTH : natural := 8
    );

    port
    (
        clk        : in std_logic;
        addr    : in natural range 0 to 2**ADDR_WIDTH - 1;
        q        : out std_logic_vector((DATA_WIDTH -1) downto 0)
    );

end entity;

architecture rtl of single_port_rom is

    -- Build a 2-D array type for the RoM
    subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
    type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;

    function init_rom
        return memory_t is
        variable tmp : memory_t := (others => (others => '0'));
    begin
        for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop
            -- Initialize each address with the address itself
            tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, DATA_WIDTH));
        end loop;
        return tmp;
    end init_rom;    

    -- Declare the ROM signal and specify a default value.    Quartus II
    -- will create a memory initialization file (.mif) based on the
    -- default value.
    signal rom : memory_t := init_rom;

begin

    process(clk)
    begin
    if(rising_edge(clk)) then
        q <= rom(addr);
    end if;
    end process;

end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rams_21b is
    generic (
        Data_w    : integer:=64;
        Data_d    : integer:=512
        );
    
    port (
        CLK     : in  std_logic;
        EN         : in  std_logic;
        ADDR     : in  std_logic_vector(8 downto 0);
        DATA     : out std_logic_vector(Data_w-1 downto 0)
    );
end rams_21b;

architecture syn of rams_21b is
    type rom_type is array (Data_d-1 downto 0) of std_logic_vector (Data_w-1 downto 0);                
    signal ROM : rom_type:= ( ТУТ 512 ОТСЧЕТОВ  );                        

signal rdata : std_logic_vector(Data_w-1 downto 0);    

begin

rdata <= ROM(conv_integer(ADDR));

process (CLK)
begin
    if (CLK'event and CLK = '1') then
        if (EN = '1') then
            DATA <= rdata;
        end if;
    end if;
end process;

end syn;