altsyncram #(
.operation_mode ("BIDIR_DUAL_PORT"),
.width_a (DATA_WIDTH_A),
.width_byteena_a (DATA_WIDTH_A / BYTE_SIZE),
.width_b (DATA_WIDTH_B),
.widthad_a (ADDR_WIDTH_A),
.widthad_b (ADDR_WIDTH_B),
.numwords_a (2**ADDR_WIDTH_A),
.numwords_b (2**ADDR_WIDTH_B),
.outdata_reg_a ("UNREGISTERED"),
.outdata_reg_b ("UNREGISTERED"),
.ram_block_type ("M9K"),
.intended_device_family ("Cyclone IV E"),
.lpm_type ("altsyncram"),
.read_during_write_mode_mixed_ports ("DONT_CARE")
)
altsyncram_inst (
.address_a (addra),
.clock0 (clka),
.clocken0 (1'b1),
.data_a (dina),
.wren_a (wea),
.byteena_a (true_bea),
.q_a (douta) ,

.address_b (addrb),
.clock1 (clkb),
.clocken1 (1'b1),
.data_b (dinb),
.wren_b (true_web),
.q_b (doutb)
);

module Mem4KTest;

// Inputs
reg clka;
reg wea;
reg [3:0] bea;
reg [10:0] addra;
reg [31:0] dina;
reg clkb;
reg web;
reg [10:0] addrb;
reg [31:0] dinb;

// Outputs
wire [31:0] douta;
wire [31:0] doutb;

// Instantiate the Unit Under Test (UUT)
TestMem_4K
uut (
.clka(clka),
.wea(wea),
.bea(bea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(clkb),
.web(web),
.addrb(addrb),
.dinb(dinb),
.doutb(doutb)
);

initial begin
// Initialize Inputs
clka = 0;
clkb = 0;

// Wait 100 ns for global reset to finish
#103;

// Add stimulus here
forever begin
clka = ~clka;
clkb = ~clkb;
#1;
#4;
end

end


integer i;
integer Correct;
integer InCorrect;

initial begin
// Initialize Inputs
wea = 0;
bea = 0;
addra = 0;
dina = 0;
web = 0;
addrb = 0;
dinb = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

bea = 4'b1111;

$display("Start write");

for(i = 0; i < 2048; i = i + 1)
begin
@(posedge clka)
begin
addra = i;
dina = i;
wea = 1;
end
@(posedge clka)
wea = 0;
@(posedge clka);
@(posedge clka);
end

@(posedge clka)
wea = 0;

$display("Start Read");


Correct = 0;
InCorrect = 0;

for(i = 0; i < 2049; i = i + 1)
begin
@(posedge clkb)
begin
if(i < 2048)
addrb = i;
#2;
if(i >= 1)
begin
if(doutb != (i-1))
begin
$display("Error %d: write %d - read %d", i , (i-1), doutb);
InCorrect = InCorrect + 1;
end
else
Correct = Correct + 1;
end
end
end



$display("Part 1, Correct %d - InCorrect %d", Correct, InCorrect);



$display("Start write");

for(i = 0; i < 2048; i = i + 1)
begin
@(posedge clkb)
begin
addrb = i;
dinb = 100*i;
@(posedge clkb)
//#2;
web = 1;
end
@(posedge clkb)
begin
//#2;
web = 0;
end
@(posedge clkb);
@(posedge clkb);
end

@(posedge clkb)
web = 0;

$display("Start Read");

Correct = 0;
InCorrect = 0;

for(i = 0; i < 2049; i = i + 1)
begin
@(posedge clka)
begin
if(i < 2048)
addra = i;
#2;
if(i >= 1)
begin
if(douta != 100*(i-1))
begin
$display("Error %d: write %d - read %d", i , 100*(i-1), douta);
InCorrect = InCorrect + 1;
end
else
Correct = Correct + 1;
end
end
end

$display("Part 2, Correct %d - InCorrect %d", Correct, InCorrect);

end


endmodule

for(i = 0; i < 2048; i = i + 1)
         begin
            @(posedge clkb)
               begin
                  addrb = i;
                  dinb = 100*i;
                  @(posedge clkb)                    -  если убрать этот такт задержки, пишутся только четные адреса, но только для порта B, для А работает и так и сяк
                  web = 1;
               end
            @(posedge clkb)
               begin
                  //#2;                                    - эта задержка не влияет
                  web = 0;
               end  
            @(posedge clkb);
            @(posedge clkb);                
         end

@(posedge clkb)
      begin
         addrb = i;
         dinb = 100*i;
         web = 1;
     end
@(posedge clkb)
     web = 0;