library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;

entity arith is
     port(
         clk : in STD_LOGIC;
         start : in STD_LOGIC;
         a : in std_logic_vector(31 downto 0);
         b : in std_logic_vector(31 downto 0);
         ready : out STD_LOGIC;
         mult : out std_logic_vector(63 downto 0)
         );
end arith;

--}} End of automatically maintained section

architecture arch of arith is
signal state:natural:=0;
begin
    process(clk)
    begin        
        if(rising_edge(clk)) then  
            if(start='1') then
                if(state=0) then  
                    state<=1;
                    ready<='0';
                end if;
            else
                if(state=1) then
                    mult<=std_logic_vector(unsigned(a)*unsigned(b));    
                    state<=2;
                end if;
                
                if(state=2) then
                    ready<='1';
                    state<=0;
                end if;
            end if;
        end if;
    end process;
     -- enter your statements here --

end arch;

library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

entity pipelined_multiplier is

-- generic size is the width of multiplier/multiplicand;
-- generic level is the intended number of stages of the
-- pipelined multiplier;
-- generic level is typically the smallest integer greater
-- than or equal to base 2 logarithm of size, as returned by
-- function log, which you define.
generic (size : integer := 32; level : integer := 1); --  level : integer := log(size)

port (
a : in std_logic_vector (size-1 downto 0);
b : in std_logic_vector (size-1 downto 0);
clk : in std_logic;
pdt : out std_logic_vector (2*size-1 downto 0));
end pipelined_multiplier;

architecture exemplar of pipelined_multiplier is
type levels_of_registers is array (level-1 downto 0) of
unsigned (2*size-1 downto 0);
signal a_int, b_int : unsigned (size-1 downto 0);
signal pdt_int : levels_of_registers;

begin
pdt <= std_logic_vector (pdt_int (level-1));

process(clk)
begin
if clk'event and clk = '1' then
-- multiplier operand inputs are registered
a_int <= unsigned (a);
b_int <= unsigned (b);
-- 'level' levels of registers to be inferred at the
-- output of the multiplier
pdt_int(0) <= a_int * b_int;
for i in 1 to level-1 loop
pdt_int (i) <= pdt_int (i-1);
end loop;
end if;
end process;
end exemplar;