module test_sdc
(
    input  bit ref_clk,
    output bit clk_out,
    output bit data_out
);


// Generate reset signal for PLL
bit[3:0] reset_cntr = '0;
bit reset_pll;
always_ff @(posedge ref_clk) begin
    if (reset_cntr != '1)
        reset_cntr <= reset_cntr + 1'b1;
end
assign reset_pll = reset_cntr != '1;

// Generate clock and reset
bit reset_n, core_clk, out_clk;
pll pll_25_200
(
  .locked   ( reset_n   ),
  .outclk_0 ( core_clk  ), // phase 0 deg
  .outclk_1 ( out_clk   ), // phase 90 deg
  .refclk   ( ref_clk   ),
  .rst      ( reset_pll )
);

// Generate data signal
bit[2:0] data_cntr;
always_ff @(posedge core_clk) begin
if (!reset_n)
  data_cntr <= '0;
else
  data_cntr <= data_cntr + 1'b1;
end
assign data_flag = data_cntr == '1;

// Create DDR output for data and clock
ddr_reg ddr_data
(
  .ck      (core_clk),
  .din     ({1'b0, data_flag}),
  .pad_out (data_out)
);

ddr_reg clk_data
(
  .ck      (out_clk),
  .din     (2'b01),
  .pad_out (clk_out)
);

endmodule

create_clock -period 25MHz [get_ports ref_clk]
derive_pll_clocks
derive_clock_uncertainty

create_generated_clock -name ext_clk_pin -source [get_pins pll_25_200|iopll_0|altera_pll_i|twentynm_pll|iopll_inst|outclk[1]] [get_ports {clk_out}]

set_output_delay -clock [get_clocks ext_clk_pin] -max  0.5 [get_ports data_out]
set_output_delay -clock [get_clocks ext_clk_pin] -min -0.5 [get_ports data_out]
set_output_delay -clock [get_clocks ext_clk_pin] -max  0.5 [get_ports data_out] -clock_fall -add_delay
set_output_delay -clock [get_clocks ext_clk_pin] -min -0.5 [get_ports data_out] -clock_fall -add_delay

set_false_path -setup  -fall_from pll_25_200|iopll_0|outclk0 -rise_to ext_clk_pin
set_false_path -setup  -rise_from pll_25_200|iopll_0|outclk0 -fall_to ext_clk_pin
set_false_path -hold   -fall_from pll_25_200|iopll_0|outclk0 -fall_to ext_clk_pin
set_false_path -hold   -rise_from pll_25_200|iopll_0|outclk0 -rise_to ext_clk_pin

set_false_path -from [all_clocks] -to [get_ports {clk_out}]

module test_sdc
(
  input  bit ref_clk,
  output bit clk_out,
  output bit data_out
);

// Generate reset signal for PLL
bit[3:0] reset_cntr = '0;
bit reset_pll;
always_ff @(posedge ref_clk) begin
    if (reset_cntr != '1)
        reset_cntr <= reset_cntr + 1'b1;
end
assign reset_pll = reset_cntr != '1;

// Generate clock and reset
bit reset_n, core_clk, out_clk, core_clk_, out_clk_;

pll pll_25_200
(
  .locked   ( reset_n   ),
  .c0       ( core_clk  ), // phase 0 deg
  .c1       ( out_clk   ), // phase 90 deg
  .inclk0   ( ref_clk   ),
  .areset   ( reset_pll )
);

// Generate data signal
bit[2:0] data_cntr;
bit data_flag;
always_ff @(posedge core_clk) begin
  if (!reset_n)
    data_cntr <= '0;
  else
    data_cntr <= data_cntr + 1'b1;
end
assign data_flag = data_cntr == '1;

// Create DDR output for data and clock
ddr_reg ddr_data
(
  .datain_h ( 1'b0      ),
  .datain_l ( data_flag ),
  .outclock ( core_clk  ),
  .dataout  ( data_out  )
);

ddr_reg clk_data
(
  .datain_h ( 1'b0      ),
  .datain_l ( 1'b1      ),
  .outclock ( out_clk   ),
  .dataout  ( clk_out   )
);

endmodule

create_clock -period 25MHz [get_ports ref_clk]
derive_pll_clocks
derive_clock_uncertainty

create_generated_clock -name ext_clk_pin -source [get_pins clk_data|ALTDDIO_OUT_component|auto_generated|ddio_outa[0]|muxsel] [get_ports {clk_out}]

set_output_delay -clock [get_clocks ext_clk_pin] -max  0.5 [get_ports data_out]
set_output_delay -clock [get_clocks ext_clk_pin] -min -0.5 [get_ports data_out]
set_output_delay -clock [get_clocks ext_clk_pin] -max  0.5 [get_ports data_out] -clock_fall -add_delay
set_output_delay -clock [get_clocks ext_clk_pin] -min -0.5 [get_ports data_out] -clock_fall -add_delay

set_false_path -setup  -fall_from pll_25_200|altpll_component|auto_generated|pll1|clk[0] -rise_to ext_clk_pin
set_false_path -setup  -rise_from pll_25_200|altpll_component|auto_generated|pll1|clk[0] -fall_to ext_clk_pin
set_false_path -hold   -fall_from pll_25_200|altpll_component|auto_generated|pll1|clk[0] -fall_to ext_clk_pin
set_false_path -hold   -rise_from pll_25_200|altpll_component|auto_generated|pll1|clk[0] -rise_to ext_clk_pin

set_false_path -from [all_clocks] -to [get_ports {clk_out}]