localparam DATA_WIDHT = 8;    //width of data bus
localparam ADDR_WIDTH = 15; //width of address bus
localparam MAX_RAM_ADDR = 1 << ADDR_WIDTH;

// main clock
input clk;

// side a
input [ADDR_WIDTH-1:0] addr_a;
input [DATA_WIDHT-1:0] data_a;
input ce_a;
input we_a;
input oe_a;
output reg[DATA_WIDHT-1:0] q_a;

// side b
input [ADDR_WIDTH-1:0] addr_b;
output reg [DATA_WIDHT-1:0] q_b;

//memory description
reg [DATA_WIDHT-1:0] mem [0:MAX_RAM_ADDR-1];

// side a read/write
always @ (posedge clk)
begin
    if (we_a) begin
        mem[addr_a] <= data_a;
    end else    begin
        q_a <= mem[addr_a];
    end
end

// side b read only
always @ (posedge clk)
begin
    q_b <= mem[addr_b];
end

endmodule

localparam MEMORY_ADDR_WIDTH = 10; //width of address in bits > 8 bits but < 16 bits
localparam MEMORY_ADDR_MAX = 1 << MEMORY_ADDR_WIDTH;
//memory description
reg [7:0] memory_r[MEMORY_ADDR_MAX-1:0]; //memory array
reg [MEMORY_ADDR_WIDTH-1:0] memory_addr_r; //current memory addr

reg [7:0] MISO_8b_r;
assign MISO_8b[7:0] = MISO_8b_r[7:0];

reg [1:0] done_r;
always @(negedge CLK) done_r[1:0] <= {done_r[0:0], DONE_8b};
wire done_risingedge = (done_r[1:0] == 2'b01);

//reg [1:0] msg_end_r;
//always @(posedge CLK) msg_end_r[1:0] <= {msg_end_r[0], MESSAGE_END};
//wire msg_end_risingedge = (msg_end_r[1:0] == 2'b01);

reg [MEMORY_ADDR_MAX-1:0] byte_count_r;
reg [0:0] rw_state; //0 - read, 1 - write

always @(posedge CLK)
begin
    if (done_risingedge)
    begin
        if (FIRST_BYTE)
        begin
            byte_count_r <= 0;
            memory_addr_r[(MEMORY_ADDR_WIDTH-1):8] <= MOSI_8b[(MEMORY_ADDR_WIDTH-9):0];
            rw_state <= MOSI_8b[7];
        end
        else
        begin
            if (byte_count_r == 0)
            begin
                memory_addr_r[7:0] <= MOSI_8b[7:0];
                byte_count_r <= byte_count_r + 1;
              
                if (rw_state == 0) //read_state
                    MISO_8b_r[7:0] <=
                        memory_r[{memory_addr_r[(MEMORY_ADDR_WIDTH-1):8],
                                  MOSI_8b[7:0]}];
            end
            else
            begin
                if (rw_state == 0) //read state
                begin
                    MISO_8b_r[7:0] <= memory_r[memory_addr_r + byte_count_r];
                end
                else //(rw_state == 1) - write state
                begin
                    memory_r[memory_addr_r + byte_count_r - 1] <= MOSI_8b[7:0];
                end
                
                byte_count_r <= byte_count_r + 1;
            end
         end
        
    end
    
/*    
    if (msg_end_risingedge)
    begin
        reg_array[reg_idx][7:0] <= reg_val[7:0];
    end
*/    
end

assign done_RE = done_risingedge;


endmodule

NET "rx_clk_in" TNM_NET = "rx_clk_in";
TIMESPEC TS_rx_clk_in = PERIOD "rx_clk_in" 20.000 ns HIGH 50%;