input signed [] A0,A1,A2;
input signed [] B0,B1,B2;

wire signed [] SA = (T == 0) ? A0 : (T == 1) ? A1 : (T == 2) ? A2 : 0;
wire signed [] SB = (T == 0) ? B0 : (T == 1) ? B1 : (T == 2) ? B2 : 0;

reg signed [] D;

always @(posedge clk)
begin
  D <= SA - SB;
end

wire [] P;

multadd multadd_m(.clk(clk),.A(D),.B(D),.C(P),.P(P));

reg [] R;

always @(posedge clk)
begin
  if (sclr)
    R <= 0;
  else
  if (valid)
    R <= P;
end

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity half_dsp_block is  
  generic (WIDTH: integer := 18);
  port (
        clock       : in  std_logic;
        areset    : in  std_logic;
        clock_ena : in  std_logic;
        a0        : in  std_logic_vector(WIDTH-1 downto 0);
        b0        : in  std_logic_vector(WIDTH-1 downto 0);
        a1        : in  std_logic_vector(WIDTH-1 downto 0);
        b1        : in  std_logic_vector(WIDTH-1 downto 0);
        a2        : in  std_logic_vector(WIDTH-1 downto 0);
        b2        : in  std_logic_vector(WIDTH-1 downto 0);
        a3        : in  std_logic_vector(WIDTH-1 downto 0);
        b3        : in  std_logic_vector(WIDTH-1 downto 0);
        w         : out std_logic_vector(2*WIDTH+1 downto 0));
end half_dsp_block;

architecture rtl of half_dsp_block is

  signal a0_reg : signed(WIDTH-1 downto 0);
  signal b0_reg : signed(WIDTH-1 downto 0);
  signal a1_reg : signed(WIDTH-1 downto 0);
  signal b1_reg : signed(WIDTH-1 downto 0);
  signal a2_reg : signed(WIDTH-1 downto 0);
  signal b2_reg : signed(WIDTH-1 downto 0);
  signal a3_reg : signed(WIDTH-1 downto 0);
  signal b3_reg : signed(WIDTH-1 downto 0);
  signal p0     : signed(2*WIDTH downto 0);
  signal p1     : signed(2*WIDTH downto 0);
  signal w_sig  : signed(2*WIDTH+1 downto 0);

begin

  process (clock, areset)
  begin
      if (areset = '1') then          -- asynchronous reset
        a0_reg <= (others => '0');
          b0_reg <= (others => '0');
          a1_reg <= (others => '0');
          b1_reg <= (others => '0');
          a2_reg <= (others => '0');
          b2_reg <= (others => '0');
          a3_reg <= (others => '0');
          b3_reg <= (others => '0');
          p0     <= (others => '0');
          p1     <= (others => '0');
          w_sig  <= (others => '0');
    elsif clock'event and clock = '1' and clock_ena = '1'then  -- rising clock edge
        a0_reg <= signed(a0);
        b0_reg <= signed(b0);
        a1_reg <= signed(a0_reg);
        b1_reg <= signed(b1);
        a2_reg <= signed(a1_reg);
        b2_reg <= signed(b2);
        a3_reg <= signed(a2_reg);
        b3_reg <= signed(b3);
        --must follow the following order to be recognized to use shift register input
        p0        <= resize((a1_reg*b1_reg),p0'length) + resize((a0_reg*b0_reg),p0'length);
        p1        <= resize((a3_reg*b3_reg),p1'length) + resize((a2_reg*b2_reg),p1'length);
        w_sig  <= resize(p0,w_sig'length) + resize(p1,w_sig'length);
    end if;
  end process;

  w <= std_logic_vector(w_sig);

end rtl;

module acc
(
    clk,
    nrst,
    A0,A1,A2,B0,B1,B2,
    T,valid,R
);

input         clk;
input         nrst;

input signed [16:0] A0,A1,A2;
input signed [16:0] B0,B1,B2;
input         [1:0] T;
input               valid;
output       [36:0] R;

wire signed [16:0] SA = (T == 0) ? A0 : (T == 1) ? A1 : (T == 2) ? A2 : 0;
wire signed [16:0] SB = (T == 0) ? B0 : (T == 1) ? B1 : (T == 2) ? B2 : 0;

reg signed [17:0] D;

always @(posedge clk)
begin
  D <= SA - SB;
end

wire [36:0] P;

dsp48mac dsp48mac_m(.clk(clk),.a(D),.b(D),.d(0),.p(P));

reg  [36:0] R;

always @(posedge clk or negedge nrst)
begin
  if (nrst == 0)
  begin
    R <= 0;
  end
  else
  if (valid)
  begin
    R <= P;
  end
end

endmodule