while (1) {

if(RD) //Проверяем сигнал отправки CRC cуммы
{
if(CLK)//Проверка положительного фронта частоты
{
if(isReady == 0)//Проверка смены такта частоты CLK
{
isReady = 1;

if(IN) // Проверка на 1 или 0 входных данных
{
miso |= mask;
}

mask <<= 1;// сдвиг маски

if(mask > 0x8000)//проверка достигла ли маска оговоренной длины
{

if(miso == 0x1D0F) {
MDR_PORTB->RXTX ^= toggle; //мигаем светодиодом
}
mask = 0x01;
miso = 0;

}
}

}
else
{
isReady = 0;
}

module CRC(

input clk,
input reset,
input data_in,
output reg RD,
output out

);

reg [15:0] lfsr_c;

reg [15:0] counter;
reg [15:0] sr;
reg [15:0] lfsr_q;
reg flag;



always @(posedge clk or negedge reset ) begin
if(!reset) begin
lfsr_q <= {16{1'b1}};
counter <= 0;
sr<=0;
flag <= 0;
end
else begin
lfsr_q <= lfsr_c;


counter <= counter + 1;

sr[14:0] <= sr[15:1];

case(counter)

15: begin sr <= 0;

if(flag) begin lfsr_q <= {16{1'b1}};
flag <= 0;
counter <= 0; end

end


32: begin sr <= lfsr_q;

end

endcase


if(counter == 33) begin
flag <= 1;
counter <= 0;
lfsr_q <= {16{1'b1}};

end//if


end
end // always

always @(negedge clk ) begin

case(counter)

15: RD<= 0;

32: RD<= 1;


endcase


end // always


always @(*) begin

lfsr_c[0] = lfsr_q[15] ^ data_in;
lfsr_c[1] = lfsr_q[0];
lfsr_c[2] = lfsr_q[1];
lfsr_c[3] = lfsr_q[2];
lfsr_c[4] = lfsr_q[3];
lfsr_c[5] = lfsr_q[4] ^ lfsr_q[15] ^ data_in;
lfsr_c[6] = lfsr_q[5];
lfsr_c[7] = lfsr_q[6];
lfsr_c[8] = lfsr_q[7];
lfsr_c[9] = lfsr_q[8];
lfsr_c[10] = lfsr_q[9];
lfsr_c[11] = lfsr_q[10];
lfsr_c[12] = lfsr_q[11] ^ lfsr_q[15] ^ data_in;
lfsr_c[13] = lfsr_q[12];
lfsr_c[14] = lfsr_q[13];
lfsr_c[15] = lfsr_q[14];




end // always



assign out = sr[0];


endmodule